ZHCSRX2 march   2023 DAC53004W

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 规格
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 详细说明
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 特性说明
      1. 7.3.1 智能数模转换器 (DAC) 架构
      2. 7.3.2 数字输入/输出
      3. 7.3.3 Nonvolatile Memory (NVM)
      4. 7.3.4 Power Consumption
    4. 7.4 器件功能模式
      1. 7.4.1 电压输出模式
        1. 7.4.1.1 电压基准和 DAC 传递函数
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 比较器模式
        1. 7.4.3.1 可编程迟滞比较器
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 故障转储模式
      5. 7.4.5 应用特定模式
        1. 7.4.5.1 电压裕量和调节
          1. 7.4.5.1.1 高阻抗输出和 PROTECT 输入
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 函数生成
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 器件复位和故障管理
        1. 7.4.6.1 上电复位 (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM 循环冗余校验 (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER 位
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT 位
      7. 7.4.7 Power-Down Mode
    5. 7.5 编程
      1. 7.5.1 SPI 编程模式
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S 模式协议
        2. 7.5.2.2 I2C 更新序列
          1. 7.5.2.2.1 地址字节
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C 读取序列
      3. 7.5.3 通用输入/输出 (GPIO) 模式
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS 寄存器（地址 = 23h）[复位 = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
      20. 7.6.20 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      21. 7.6.21 PMBUS-PAGE Register [reset = 0300h]
      22. 7.6.22 PMBUS-OP-CMD-X Register [reset = 0000h]
      23. 7.6.23 PMBUS-CML Register [reset = 0000h]
      24. 7.6.24 PMBUS-VERSION 寄存器 [复位 = 2200h]
  8. 8 应用和实现
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 布局
      1. 8.4.1 布局指南
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]

PMBus page address = FFh, PMBus register address = E8h

Figure 7-37 GPIO-CONFIG Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GF-EN DEEP-SLEEP-EN GPO-EN GPO-CONFIG GPI-CH-SEL GPI-CONFIG GPI-EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 7-38 GPIO-CONFIG Register Field Descriptions
Bit Field Type Reset Description
15 GF-EN R/W 0 0: Glitch filter disabled for GP input. This setting provides faster response.
1: Glitch filter enabled for GP input. This setting introduces additional propagation delay but provides robustness.
14 DEEP-SLEEP-EN R/W 0 0: Deep-sleep mode disabled
1: Deep-sleep mode enabled for GP input
13 GPO-EN R/W 0 0: Disable output mode for GPIO pin
1: Enable output mode for GPIO pin
12-9 GPO-CONFIG R/W 0000 STATUS function setting. The GPIO pin is mapped to the following register bits as output:
0001: NVM-BUSY
0100: DAC-0-BUSY
0101: DAC-1-BUSY
0110: DAC-2-BUSY
0111: DAC-3-BUSY
1000: WIN-CMP-0
1001: WIN-CMP-1
1010: WIN-CMP-2
1011:WIN-CMP-3
Others: Invalid
8-5 GPI-CH-SEL R/W 0000 Each bit corresponds to a DAC channel. 0b is disabled and 1b is enabled.
GPI-CH-SEL[0]: Channel 0
GPI-CH-SEL[1]: Channel 1
GPI-CH-SEL[2]: Channel 2
GPI-CH-SEL[3]: Channel 3Example: when GPI-CH-SEL is 0101, both channel-0 and channel-2 are enabled and both channel-1 and channel-3 are disabled.
4-1 GPI-CONFIG R/W 0000 GPIO pin input configuration. Global settings act on the entire device. Channel-specific settings depend on the channel selection by the GPI-CH-SEL bits:0000: DEEP-SLEEP (global). GPIO falling-edge triggers deep-sleep mode, GPIO rising-edge takes the device out of deep-sleep mode.0010: FAULT-DUMP (global). GPIO falling-edge triggers fault-dump, GPIO = 1 has no effect.0011: IOUT power-up, down (channel-specific). GPIO falling-edge triggers power-down, GPIO rising-edge triggers power-up.0100: VOUT power-up/down (channel-specific). The output load is as per the VOUT-PDN-X setting. GPIO falling-edge triggers power-down, GPIO rising-edge triggers power-up.0101: PROTECT input (global). GPIO falling-edge asserts PROTECT function, GPIO = 1 has no effect.0111: CLR input (global). GPIO = 0 asserts CLR function, GPIO = 1 has no effect.1000: LDAC input (channel-specific). GPIO falling-edge asserts LDAC function, GPIO = 1 has no effect. Both the SYNC-CONFIG-X and the GPI-CH-SEL must be configured for every channel.1001: Start, stop function generation (channel-specific). GPIO falling-edge stops function generation. GPIO rising-edge starts function generation.1010: Trigger margin-high, low (channel-specific). GPIO falling-edge triggers margin-low. GPIO rising-edge triggers margin-high.1011: RESET input (global). The falling-edge of the GPIO pin asserts the RESET function. The RESET input must be a pulse. The GPIO rising-edge brings the device out of reset. The RESET configuration must be programmed into the NVM. Otherwise, the setting is cleared after the device reset. 1100: NVM write-protection (global). GPIO falling-edge allows NVM programming. GPIO rising-edge blocks NVM programming.1101: Register-map lock (global). GPIO falling-edge allows update to the register map. GPIO rising-edge blocks any register map update except a write to the DEV-UNLOCK field through I2C or SPI and to the RESET field through I2C.Others: Not applicable
0 GPI-EN R/W 0 0: Disable input mode for GPIO pin
1: Enable input mode for GPIO pin