ZHCSOM0 October   2020 DAC43401-Q1 , DAC53401-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Standard Mode
    7. 7.7  Timing Requirements: I2C Fast Mode
    8. 7.8  Timing Requirements: I2C Fast Mode Plus
    9. 7.9  Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    10. 7.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 Reference Selection and DAC Transfer Function
          1. 8.3.1.1.1 Power Supply as Reference
          2. 8.3.1.1.2 Internal Reference
      2. 8.3.2 DAC Update
        1. 8.3.2.1 DAC Update Busy
      3. 8.3.3 Nonvolatile Memory (EEPROM or NVM)
        1. 8.3.3.1 NVM Cyclic Redundancy Check
        2. 8.3.3.2 NVM_CRC_ALARM_USER Bit
        3. 8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit
      4. 8.3.4 Programmable Slew Rate
      5. 8.3.5 Power-on-Reset (POR)
      6. 8.3.6 Software Reset
      7. 8.3.7 Device Lock Feature
      8. 8.3.8 PMBus Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down Mode
      2. 8.4.2 Continuous Waveform Generation (CWG) Mode
      3. 8.4.3 PMBus Compatibility Mode
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 I2C Update Sequence
        1. 8.5.2.1 Address Byte
        2. 8.5.2.2 Command Byte
      3. 8.5.3 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1 STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 8.6.2 GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 8.6.3 TRIGGER Register (address = D3h) [reset = 0008h]
      4. 8.6.4 DAC_DATA Register (address = 21h) [reset = 0000h]
      5. 8.6.5 DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
      6. 8.6.6 DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
      7. 8.6.7 PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      8. 8.6.8 PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      9. 8.6.9 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Power-Supply Margining
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 说明

10 位 DAC53401-Q1 和 8 位 DAC43401-Q1 (DACx3401-Q1) 是具有引脚兼容性的汽车类缓冲电压输出智能数模转换器 (DAC) 系列产品。这些器件功耗极低且均可采用微型 8 引脚 WSON 封装。凭借这组特性以及微型封装和低功耗，DACx3401-Q1 非常适合以下应用：LED 和通用偏置点生成、电源控制和 PWM 信号生成。

这些器件具有非易失性存储器 (NVM)、一个内部基准和一个兼容 PMBus 的 I2C 接口。DACx3401-Q1 在内部基准或电源基准下运行，提供 1.8V 至 5.5V 的满量程输出。该器件通过 I2C 接口通信。这些器件支持 I2C 标准模式、快速模式和快速+ 模式。

DACx3401-Q1 是智能 DAC 器件，因为它们具有高级集成特性。这些智能 DAC 具有强制检测输出、PWM 输出和 NVM 功能，无需使用软件即可实现系统性能和控制功能。

器件信息
器件型号(1) 封装 封装尺寸（标称值）
DAC53401-Q1 WSON (8) 2.00mm × 2.00mm
DAC43401-Q1
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

 

GUID-20201012-CA0I-GNDW-Z1JK-TCQPZDVFXSZQ-low.gif功能方框图
GUID-20201012-CA0I-PLZR-KTW7-5LKR8WPQ4HWB-low.gif使用 DACx3401-Q1 的 LED 偏置