ZHCS964E February   2012  – September 2015 DAC34SH84

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements - Digital Specifications
    9. 6.9  Switching Characteristics - AC Specifications
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
      3. 7.3.3  Data Format
      4. 7.3.4  Input FIFO
      5. 7.3.5  FIFO Modes of Operation
        1. 7.3.5.1 Dual-Sync-Sources Mode
        2. 7.3.5.2 Single-Sync-Source Mode
        3. 7.3.5.3 Bypass Mode
      6. 7.3.6  Clocking Modes
        1. 7.3.6.1 PLL Bypass Mode
        2. 7.3.6.2 PLL Mode
      7. 7.3.7  FIR Filters
      8. 7.3.8  Complex Signal Mixer
        1. 7.3.8.1 Full Complex Mixer
        2. 7.3.8.2 Coarse Complex Mixer
        3. 7.3.8.3 Mixer Gain
        4. 7.3.8.4 Real Channel Upconversion
      9. 7.3.9  Quadrature Modulation Correction (QMC)
        1. 7.3.9.1 Gain and Phase Correction
        2. 7.3.9.2 Offset Correction
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Data Pattern Checker
      12. 7.3.12 Parity Check Test
        1. 7.3.12.1 32-Bit Parity
        2. 7.3.12.2 Dual 16-Bit Parity
      13. 7.3.13 DAC34SH84 Alarm Monitoring
      14. 7.3.14 LVPECL Inputs
      15. 7.3.15 LVDS Inputs
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
        1. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 7.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
        1. 7.5.2.1 Device Configuration
        2. 7.5.2.2 PLL Configuration
        3. 7.5.2.3 NCO Configuration
        4. 7.5.2.4 Example Start-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Data Input Rate
          2. 8.2.1.2.2 Interpolation
          3. 8.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Data Input Rate
          2. 8.2.2.2.2 Interpolation
          3. 8.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Assembly
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 器件命名规则
        1. 11.1.2.1 技术参数定义
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 器件命名规则

11.1.2.1 技术参数定义

邻载波泄漏比 (ACLR)：为与峰值平均比为 12dB 的载波之间存在 5MHz 偏移的 3.84MHz 带宽中测得的 3.84Mcps 3GPP W-CDMA 输入信号而定义

模拟和数字电源抑制比（APSSR 和 DPSSR）：定义为 IOUT 变化量与相对于 IOUT 电流理想值标准化的电源电压变化量之比的百分比误差

微分非线性 (DNL)：定义为数字输入编码变化 1 LSB（理想值）时对应的模拟输出变化

增益漂移：定义为环境温度 (25°C) 下的增益值与整个工作温度范围内的增益值之间的最大变化量（以 ppm/°C 为单位，相对于满量程范围 (FSR)）

增益误差：定义为测得的满量程输出电流与理想的满量程输出电流之比的百分比误差 (FSR%)

积分非线性 (INL)：定义为实际模拟输出与理想输出的最大偏差，取决于在零与满量程刻度之间绘制的直线

互调失真 (IMD3)：双频 IMD3 定义为三阶互调失真与任一基频输出之比（以 dBc 为单位）

偏移漂移：定义为环境温度 (25°C) 下的直流偏移值与整个工作温度范围内的直流偏移值之间的最大变化量（以 ppm/°C 为单位，相对于满量程范围 (FSR)）

偏移误差：定义为测得的中档输出电流与理想的中档输出电流之比的百分比误差 (FSR%)

输出合规范围：定义为电流输出 DAC 的输出端允许的最低电压和最高电压。超出此限制范围可能导致器件可靠性降低，或者对失真性能产生不利影响。

基准电压漂移：定义为环境温度 (25°C) 下的基准电压值与整个工作温度环境范围内的基准电压值之间的最大变化量（以 ppm/°C 为单位）

无杂散动态范围 (SFDR)：定义为输出信号的峰值与第一奈奎斯特区域内的峰值杂散信号之差（以 dBc 为单位）

噪声频谱密度 (NSD)：定义为输出音调信号功率与第一奈奎斯特区域内的 1Hz 带宽噪底之间的功率差（以 dBc 为单位）

11.2 文档支持

11.2.1 相关文档

  • 《DAC34H84 EVM 用户指南》（文献编号：SLAU338）
  • 应用报告《nFBGA 封装》（文献编号：SPRAA99）

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

esds-image

这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.