ZHCSTF3H June   2007  – February 2024 CDCE913 , CDCEL913

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-up
        4. 8.2.2.4 Frequency Adjustment with Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs/Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.1 SDA/SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and explanations describe the programmable functions of the CDCE913 or CDCEL913. All settings can be manually written into the device through the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for optimized performance at lowest jitter.

Table 9-1 SDA/SCL Registers
ADDRESS OFFSETREGISTER DESCRIPTIONTABLE
00hGeneric configuration registerTable 9-3
10hPLL1 configuration registerTable 9-4

The grey-highlighted bits, described in the configuration register tables in the following pages, belong to the control terminal register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2. See Control Terminal Configuration.

Table 9-2 Configuration Register, External Control Terminals
Y1 PLL1 Settings
EXTERNAL CONTROL PINS OUTPUT SELECTION FREQUENCY SELECTION SSC SELECTION OUTPUT SELECTION
S2 S1 S0 Y1 FS1 SSC1 Y2Y3
0 0 0 0 Y1_0 FS1_0 SSC1_0 Y2Y3_0
1 0 0 1 Y1_1 FS1_1 SSC1_1 Y2Y3_1
2 0 1 0 Y1_2 FS1_2 SSC1_2 Y2Y3_2
3 0 1 1 Y1_3 FS1_3 SSC1_3 Y2Y3_3
4 1 0 0 Y1_4 FS1_4 SSC1_4 Y2Y3_4
5 1 0 1 Y1_5 FS1_5 SSC1_5 Y2Y3_5
6 1 1 0 Y1_6 FS1_6 SSC1_6 Y2Y3_6
7 1 1 1 Y1_7 FS1_7 SSC1_7 Y2Y3_7
Address offset(1) 04h 13h 10h–12h 15h
(1) Address offset refers to the byte address in the configuration register in Table 9-3 and Table 9-4.
Table 9-3 Generic Configuration Register
OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
00h 7 E_EL Xb Device identification (read-only): 1 is CDCE913 (3.3 V out), 0 is CDCEL913 (1.8 V out)
6:4 RID Xb Revision identification number (read-only)
3:0 VID 1h Vendor identification number (read-only)
01h 7 – 0b Reserved – always write 0
6 EEPIP 0b EEPROM programming Status4:(4) (read-only) 0 – EEPROM programming is completed.
1 – EEPROM is in programming mode.
5 EELOCK 0b Permanently lock EEPROM data(5) 0 – EEPROM is not locked.
1 – EEPROM is permanently locked.
4 PWDN 0b Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – Device active (PLL1 and all outputs are enabled)
1 – Device power down (PLL1 in power down and all outputs in 3-state)
3:2 INCLK 00b Input clock selection: 00 – Xtal     10 – LVCMOS
01 – VCXO 11 – Reserved
1:0 TARGET_ADR 01b Address bits A0 and A1 of the target receiver address
02h 7 M1 1b Clock source selection for output Y1: 0 – Input clock  1 – PLL1 clock
6 SPICON 0b Operation mode selection for pin 12/13(6)
0 – Serial programming interface SDA (pin 13) and SCL (pin 12)
1 – Control pins S1 (pin 13) and S2 (pin 12)
5:4 Y1_ST1 11b Y1-State0/1 definition
3:2 Y1_ST0 01b 00 – Device power down (all PLLs in power down and all outputs in 3-State)
01 – Y1 disabled to 3-state		 10 – Y1 disabled to low
11 – Y1 enabled
1:0 Pdiv1 [9:8] 001h 10-bit Y1-output-divider Pdiv1: 0 – Divider reset and stand-by
1 to 1023 – Divider value
03h 7:0 Pdiv1 [7:0]
04h 7 Y1_7 0b Y1_x State Selection(7) 0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
6 Y1_6 0b
5 Y1_5 0b
4 Y1_4 0b
3 Y1_3 0b
2 Y1_2 0b
1 Y1_1 1b
0 Y1_0 0b
05h 7:3 XCSEL 0Ah Crystal load capacitor selection(8) 00h – 0 pF
01h – 1 pF
02h – 2 pF
:14h to 1Fh – 20 pF
2:0 0b Reserved – do not write other than 0
06h 7:1 BCOUNT 20h 7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes must be read out to finish the read cycle correctly.
0 EEWRITE 0b Initiate EEPROM write cycle (4)(9) 0– No EEPROM write cycle
1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)
07h-0Fh — 0h Unused address range
(1) Writing data beyond ‘20h may affect device function.
(2) All data transferred with the MSB first
(3) Unless customer-specific setting
(4) During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).
(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible. Data, however can still be written through the SDA/SCL bus to the internal register to change device function on the fly, but new data can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.
(6) Selection of control pins is effective only if written into the EEPROM. After the pins are written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporarily act as serial programming pins (SDA/SCL), and the two target receiver address bits are reset to A0 = 0 and A1 = 0.
(7) These are the bits of the control terminal register (see Table 9-2 ). The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF. For CL > 20 pF, use additional external capacitors. The device input capacitance value must be considered, which always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more about VCXO config. and crystal recommendation, see application report SCAA085.
(9) The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
Table 9-4 PLL1 Configuration Register
OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
10h 7:5 SSC1_7 [2:0] 000b SSC1: PLL1 SSC selection (modulation amount). (4)
4:2 SSC1_6 [2:0] 000b Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		 Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0 SSC1_5 [2:1] 000b
11h 7 SSC1_5 [0]
6:4 SSC1_4 [2:0] 000b
3:1 SSC1_3 [2:0] 000b
0 SSC1_2 [2] 000b
12h 7:6 SSC1_2 [1:0]
5:3 SSC1_1 [2:0] 000b
2:0 SSC1_0 [2:0] 000b
13h 7 FS1_7 0b FS1_x: PLL1 frequency selection(4)
6 FS1_6 0b 0 – fVCO1_0 (predefined by PLL1_0 – multiplier/divider value)
1 – fVCO1_1 (predefined by PLL1_1 – multiplier/divider value)
5 FS1_5 0b
4 FS1_4 0b
3 FS1_3 0b
2 FS1_2 0b
1 FS1_1 0b
0 FS1_0 0b
14h 7 MUX1 1b PLL1 multiplexer: 0 – PLL1
1 – PLL1 bypass (PLL1 is in power down)
6 M2 1b Output Y2 multiplexer: 0 – Pdiv1
1 – Pdiv2
5:4 M3 10b Output Y3 Multiplexer: 00 – Pdiv1-divider
01 – Pdiv2-divider
10 – Pdiv3-divider
11 – Reserved
3:2 Y2Y3_ST1 11b Y2, Y3-State0/1definition: 00 – Y2/Y3 disabled to 3-state (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
1:0 Y2Y3_ST0 01b
15h 7 Y2Y3_7 0b Y2Y3_x output state selection. (4)
6 Y2Y3_6 0b 0 – State0 (predefined by Y2Y3_ST0)
1 – State1 (predefined by Y2Y3_ST1)
5 Y2Y3_5 0b
4 Y2Y3_4 0b
3 Y2Y3_3 0b
2 Y2Y3_2 0b
1 Y2Y3_1 1b
0 Y2Y3_0 0b
16h 7 SSC1DC 0b PLL1 SSC down/center selection: 0 – Down
1 – Center
6:0 Pdiv2 01h 7-bit Y2-output-divider Pdiv2: 0 – Reset and stand-by
1 to 127 – Divider value
17h 7 — 0b Reserved – do not write others than 0
6:0 Pdiv3 01h 7-bit Y3-output-divider Pdiv3: 0 – Reset and stand-by
1 to 127 – Divider value
18h 7:0 PLL1_0N [11:4] 004h PLL1_0(5): 30-bit multiplier/divider value for frequency fVCO1_0
(for more information, see the PLL Multiplier/Divider Definition paragraph).
19h 7:4 PLL1_0N [3:0]
3:0 PLL1_0R [8:5] 000h
1Ah 7:3 PLL1_0R[4:0]
2:0 PLL1_0Q [5:3] 10h
1Bh 7:5 PLL1_0Q [2:0]
4:2 PLL1_0P [2:0] 010b
1:0 VCO1_0_RANGE 00b fVCO1_0 range selection: 00 – fVCO1_0 < 125 MHz
01 – 125 MHz ≤ fVCO1_0 < 150 MHz
10 – 150 MHz ≤ fVCO1_0 < 175 MHz
11 – fVCO1_0 ≥ 175 MHz
1Ch 7:0 PLL1_1N [11:4] 004h PLL1_1(5): 30-bit multiplier/divider value for frequency fVCO1_1
(for more information see the PLL Multiplier/Divider Definition).
1Dh 7:4 PLL1_1N [3:0]
3:0 PLL1_1R [8:5] 000h
1Eh 7:3 PLL1_1R[4:0]
2:0 PLL1_1Q [5:3] 10h
1Fh 7:5 PLL1_1Q [2:0]
4:2 PLL1_1P [2:0] 010b
1:0 VCO1_1_RANGE 00b fVCO1_1 range selection: 00 – fVCO1_1 < 125 MHz
01 – 125 MHz ≤ fVCO1_1 < 150 MHz
10 – 150 MHz ≤ fVCO1_1 < 175 MHz
11 – fVCO1_1 ≥ 175 MHz
(1) Writing data beyond 20h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096