ZHCSKT0I
November 1998 – May 2024
CD4066B
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
接收文档更新通知
9.2
支持资源
9.3
Trademarks
9.4
静电放电警告
9.5
术语表
10
Revision History
11
Mechanical, Packaging, and Orderable Information
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
D|14
PW|14
N|14
NS|14
散热焊盘机械数据 (封装 | 引脚)
PW|14
QFND305D
D|14
QFND304D
订购信息
zhcskt0i_oa
zhcskt0i_pm
6
Parameter Measurement Information
Figure 6-1
Determination of r
on
as a Test Condition for Control-Input High-Voltage (V
IHC
) Specification
Figure 6-2
Channel On-State Resistance Measurement Circuit
Figure 6-3
Typical On Characteristics for One of Four Channels
Figure 6-4
Off-Switch Input or Output Leakage
Figure 6-5
Propagation Delay Time Signal Input (V
is
) to Signal Output (V
os
)
Figure 6-6
Crosstalk-Control Input to Signal Output
All unused pins are connected to V
SS
.
Delay is measured at V
os
level of +10% from ground (turn-on) or on-state output level (turn-off).
Figure 6-7
Propagation Delay, t
PLH
, t
PHL
Control-Signal Output
All unused pins are connected to V
SS
.
Figure 6-8
Maximum Allowable Control-Input Repetition Rate
Figure 6-9
Input Leakage-Current Test Circuit
Figure 6-10
Four-Channel PAM Multiplex System Diagram