ZHCSKT0H November   1998  – February 2020 CD4066B

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     通过数字控制逻辑进行双向信号传输
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • D|14
  • PW|14
  • N|14
  • NS|14
散热焊盘机械数据 (封装 | 引脚)
订购信息

Functional Block Diagram

CD4066B Schematic_1_SCHS051.gif
All control inputs are protected by the CMOS protection network.
All p substrates are connected to VDD.
Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS.
Signal-level range: VSS ≤ Vis ≤ VDD.
Figure 17. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry