ZHCSK48D February   2019  – May 2021 CC3135MOD

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3135MOD Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
      1.      12
    4. 7.4 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Current Consumption Summary: 2.4 GHz RF Band
    5. 8.5  Current Consumption Summary: 5 GHz RF Band
    6. 8.6  TX Power Control for 2.4 GHz Band
    7. 8.7  TX Power Control for 5 GHz Band
    8. 8.8  Brownout and Blackout Conditions
    9. 8.9  Electrical Characteristics for DIO Pins
    10. 8.10 WLAN Receiver Characteristics
      1.      25
      2.      26
    11. 8.11 WLAN Transmitter Characteristics
      1.      28
      2.      29
    12. 8.12 BLE and WLAN Coexistence Requirements
    13. 8.13 Reset Requirement
    14. 8.14 Thermal Resistance Characteristics for MOB Package
    15. 8.15 Timing and Switching Characteristics
      1. 8.15.1 Power-Up Sequencing
      2. 8.15.2 Power-Down Sequencing
      3. 8.15.3 Device Reset
      4. 8.15.4 Wakeup From HIBERNATE Mode Timing
    16. 8.16 External Interfaces
      1. 8.16.1 SPI Host Interface
      2. 8.16.2 Host UART Interface
        1. 8.16.2.1 5-Wire UART Topology
        2. 8.16.2.2 4-Wire UART Topology
        3. 8.16.2.3 3-Wire UART Topology
      3. 8.16.3 External Flash Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Module Features
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
        1. 9.2.2.1 Security
      3. 9.2.3 FIPS 140-2 Level 1 Certification
      4. 9.2.4 Host Interface and Driver
      5. 9.2.5 System
    3. 9.3  Power-Management Subsystem
      1. 9.3.1 VBAT Wide-Voltage Connection
    4. 9.4  Low-Power Operating Modes
      1. 9.4.1 Low-Power Deep Sleep
      2. 9.4.2 Hibernate
      3. 9.4.3 Shutdown
    5. 9.5  Restoring Factory Default Configuration
    6. 9.6  Hostless Mode
    7. 9.7  Device Certification and Qualification
      1. 9.7.1 FCC Certification and Statement
      2. 9.7.2 IC/ISED Certification Statement
      3. 9.7.3 ETSI/CE Certification
      4. 9.7.4 Japan MIC Certification
    8. 9.8  Module Markings
    9. 9.9  End Product Labeling
    10. 9.10 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
      4. 10.1.4 Power Supply Decoupling and Bulk Capacitors
      5. 10.1.5 Reset
      6. 10.1.6 Unused Pins
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General Layout Recommendations
      2. 10.2.2 RF Layout Recommendations
      3. 10.2.3 Antenna Placement and Routing
      4. 10.2.4 Transmission Line Considerations
  11. 11Environmental Requirements and SMT Specifications
    1. 11.1 Temperature
      1. 11.1.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 PCB Assembly Guide
      1. 11.4.1 PCB Land Pattern & Thermal Vias
      2. 11.4.2 SMT Assembly Recommendations
      3. 11.4.3 PCB Surface Finish Requirements
      4. 11.4.4 Solder Stencil
      5. 11.4.5 Package Placement
      6. 11.4.6 Solder Joint Inspection
      7. 11.4.7 Rework and Replacement
      8. 11.4.8 Solder Joint Voiding
    5. 11.5 Baking Conditions
    6. 11.6 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Development Tools and Software
    3. 12.3 Firmware Updates
    4. 12.4 Documentation Support
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 Export Control Notice
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information
        1. 13.2.2.1 Tape Specifications

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

7.2 Pin Attributes

Table 7-1 describes the CC3135MOD pins.

Note:

Digital IOs on the CC3135MOD refer to hostless mode, BLE/2.4 GHz coexistence, and antenna select IOs, not general-purpose IOs.

If an external device drives a positive voltage to signal pads when the CC3135MOD is not powered, DC current is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3135MOD device can occur. To prevent current draw, TI recommends one of the following:

  • All devices interfaced to the CC3135MOD must be powered from the same power rail as the CC3135MOD device.
  • Use level shifters between the CC3135MOD and any external devices fed from other independent rails.
  • The nRESET pin of the CC3135MOD device must be held low until the VBAT supply to the device is driven and stable.
Table 7-1 Pin Description and Attributes
PIN DEFAULT FUNCTION DIGITAL I/O STATE AT RESET AND HIBERNATE I/O TYPE(1) CC3135 DEVICE PIN NO. DESCRIPTION
HOSTLESS MODE BLE COEX
CC_COEX_ OUT CC_COEX_ IN
1 GND N/A N/A N/A – Power - GND
2 GND N/A N/A N/A – Power - GND
3 DIO10 Y Y Y – I/O 1 Digital input or output
4 nHIB - - - Hi-Z I 2 Hibernate signal input to the NWP subsystem (active low). This is connected to the MCU GPIO. If the GPIO from the MCU can float while the MCU enters low power, consider adding a pullup resistor on the board to avoid floating.
5 HOST_SPI_CLK - - - Hi-Z I 5 Host interface SPI clock
6 HOST_SPI_MOSI - - - Hi-Z I 6 Host interface SPI data input
7 HOST_SPI_MISO - - - Hi-Z O 7 Host interface SPI data output
8 HOST_SPI_nCS - - - Hi-Z I 8 Host interface SPI chip select (active low)
9 DIO12 Y Y Y – O 3 Digital input or output
10 DIO13 Y Y Y – – 4 Digital input or output
11 HOST_INTR - - - Hi-Z O 15 Interrupt output (active high)
12 DIO23 Y Y Y Hi-Z 16 Digital input or output
13 FLASH _SPI_MISO N/A N/A N/A Hi-Z I - External Serial Flash Programming: SPI data in
14 FLASH _SPI_CS N/A N/A N/A Hi-Z O - External Serial Flash Programming: SPI chip select (active low)
15 FLASH_SPI_CLK N/A N/A N/A Hi-Z O - External Serial Flash Programming: SPI clock
16 GND N/A N/A N/A – Power - Ground
17 FLASH_SPI_MOSI N/A N/A N/A Hi-Z O - External Serial Flash Programming: SPI data out
18 DIO24 Y Y Y Hi-Z 17 Digital input or output
19 DIO28 Y Y Y – – 18 Digital input or output
20 NC N/A N/A N/A – – - No Connect
21 Reserved - - - Hi-Z – - No Connect
22 DIO29 Y Y Y Hi-Z 20 Digital input or output
23 SOP2 Y(2) Y - Hi-Z O 21 A 100 kΩ pull down resistor is internally tied to this SOP pin.
24 SOP1 N/A N/A N/A Hi-Z – 34 A 100 kΩ pull down resistor is internally tied to this SOP pin. SOP[2:0] used for factory restore. See Section 9.5.
25 GND N/A N/A N/A – Power - GND
26 GND N/A N/A N/A – Power - GND
27 GND N/A N/A N/A – Power - GND
28 GND N/A N/A N/A – Power - GND
29 GND N/A N/A N/A – Power - GND
30 GND N/A N/A N/A – Power - GND
31 RF_ABG N/A N/A N/A Hi-Z RF 27, 28, 31 2.4 GHz & 5 GHz RF TX, RX
32 GND N/A N/A N/A – Power - GND
33 NC N/A N/A N/A – – - No Connect
34 SOP0 N/A N/A N/A Hi-Z – 35 A 100 kΩ pull down resistor is internally tied to this SOP pin. SOP[2:0] used for factory restore. See Section 9.5.
35 nRESET N/A N/A N/A Hi-Z I 32 There is an internal 100 kΩ pull-up resistor option from the nRESET pin to VBAT_RESET. Note: VBAT_RESET is not connected to VBAT1 or VBAT2 within the module. The following connection schemes are recommended:
  • Connect nRESET to a GPIO from the host only if nRESET will be in a defined state under all operating conditions. Leave VBAT_RESET unconnected to save power.
  • If nRESET cannot be in a defined state under all operating conditions, connect VBAT_RESET to the main module power supply (VBAT1 and VBAT2). Due to the internal pull-up resistor, a leakage current of 3.3 V / 100 kΩ is expected.
36 VBAT_RESET N/A N/A N/A Hi-Z - 37
37 VBAT1 N/A N/A N/A Hi-Z - 39 Power supply for the module, must be connected to battery (2.3 V to 3.6 V)
38 GND N/A N/A N/A – Power - GND
39 NC N/A N/A N/A – – - No Connect
40 VBAT2 N/A N/A N/A Hi-Z - 10, 44, 54 Power supply for the module, must be connected to battery (2.3 V to 3.6 V)
41 NC N/A N/A N/A – – - No Connect
42 DIO30 Y Y Y Hi-Z – 53 Network Scripter I/O
43 GND N/A N/A N/A – Power - GND
44 UART1_nRTS - - - Hi-Z O 50 UART interface to host (request to send)
45 NC N/A N/A N/A – – - No Connect
46 UART1_TX - - - Hi-Z O 55 UART interface to host (transmit)
47 UART1_RX - - - Hi-Z I 57 UART interface to host (receive)
48 TEST_58 Y Y Y Hi-Z O 58 Test signal; connect to an external test point.
49 TEST_59 Y Y Y Hi-Z O 59 Test signal; connect to an external test point.
50 TEST_60 Y Y Y Hi-Z O 60 Test signal; connect to an external test point.
51 UART1_nCTS - - - Hi-Z I 61 UART interface to host (clear to send)
52 TEST_62 - - - Hi-Z O 62 Test signal; connect to an external test point.
53 DIO8 Y Y Y Hi-Z 63 Digital input or output
54 DIO9 Y Y Y Hi-Z – 64 Digital input or output
(1) I = input, O = output, RF = radio frequency, I/O = bidirectional
(2) Output Only