ZHCSGR7 September 2017
PRODUCTION DATA.
The bq25600C device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-polymer battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate drive.
The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.
If only battery is present and the voltage is above depletion threshold (VBAT_DPL_RISE), the BATFET turns on and connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the bias circuits. It detects and sets the input current limit before the buck converter is started. The power up sequence from input source is as listed:
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN is enabled when all the below conditions are valid:
If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device is in HIZ.
After REGN LDO powers up, the device confirms the current capability of the input source. The input source must meet both of the following requirements in order to start the buck converter.
Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.
After the VBUS_GD bit is set and REGN LDO is powered, the device runs input source detection through PSEL pin. The bq25600C sets input current limit through PSEL pins.
After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following registers and pin are changed:
The host can over-write IINDPM register to change the input current limit if needed. The charger input current is always limited by the IINDPM register.
The bq25600C has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB PHY device output to decide whether the input is USB host or charging port. When the device operates in host-control mode, the host needs to IINDET_EN bit to read the PSEL value and update the IINDPM register. When the device is in default mode, PSEL value updates IINDPM in real time.
Input Detection | PSEL Pin | INPUT CURRENT LIMIT (ILIM) | VBUS_STAT |
---|---|---|---|
USB SDP | High | 500 mA | 001 |
Adapter | Low | 2.4 A | 011 |
The device supports wide range of input voltage limit (3.9 V – 5.4 V) for USBThe device's VINDPM is set at 4.5 V. The device supports dynamic VINDPM trackingsettings which tracks the battery voltage. This function can be enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the actual input voltage limit will be the higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input current is limited to is to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the device limits input current to the value set by IINDPM register.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design.
The device switches to PFM control at light load or when battery is below minimum system voltage setting or charging is disabled. The PFM_DIS bit can be used to prevent PFM operation in either buck configuration.
The bq25600C is a host controlled charger, but it can operate in default mode without host management. In default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode, WATCHDOG_FAULT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the registers are in the default settings. During default mode, any change on PSEL pin will make real time IINDPM register changes.
in default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end of the 10-hour, the charging is stopped and the buck converter continues to operate to supply system load.
Writing a 1 to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.
When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all registers are reset to default values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and BATFET_DIS bits.
The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both.
The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5-mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.
With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously completes a charging cycle without host involvement. The device default charging parameters are listed in Table 2. The host can always control the charging operations and optimize the charging parameters by writing to the corresponding registers through I2C.
PARAMETER | SETTING |
---|---|
Charging voltage | 4.208 V |
Charging current | 2.048 A |
Pre-charge current | 180 mA |
Termination current | 180 mA |
Safety timer | 10 hours |
A new charge cycle starts when the following conditions are valid:
The charger device automatically terminates the charging cycle when the charging current is below termination threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation. When a fully charged battery is discharged below recharge threshold (selectable through VRECHG bit), the device automatically starts a new charging cycle. After the charge is done, toggle CE pin or CHG_CONFIG bit can initiate a new charging cycle.
The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The STAT output can be disabled by setting EN_ICHG_MON bits = 11. in addition, the status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an INT is asserted to notify the host.
The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage and regulates current and voltage accordingly.
VBAT | CHARGinG CURRENT | REGISTER DEFAULT SETTinG | CHRG_STAT |
---|---|---|---|
< 2.2 V | ISHORT | 100 mA | 01 |
2.2 V to 3 V | IPRECHG | 180 mA | 01 |
> 3 V | ICHG | 2.048 A | 10 |
If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. in this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host. Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation. Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
At low termination currents (25 mA-50 mA), due to the comparator offset, the actual termination current may be 10 mA-20 mA higher than the termination target. in order to compensate for comparator offset, a programmable top-off timer can be applied after termination is detected. The termination timer will follow safety timer constraints, such that if safety timer is suspended, so will the termination timer. Similarly, if safety timer is doubled, so will the termination timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The host can read CHRG_STAT and TOPOFF_ACTIVE to find out the termination status.
Top off timer gets reset at one of the following conditions:
The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host when entering top-off timer segment as well as when top-off timer expires.
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 2 hours when the battery is below VBATLOWV threshold and 10 hours when the battery is higher than VBATLOWV threshold.
The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be disabled through I2C by setting EN_TIMER bit
During input voltage, current, or thermal regulation, the safety timer counts at half clock rate as the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.
During the fault, timer is suspended. Once the fault goes away, fault resumes. If user stops the current charging cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by SYS_Min bits. Even with a fully depleted battery, the system is regulated above the minimum system voltage.
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET.
When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the system is always regulated at typically 50mV above battery voltage. The status register VSYS_STAT bit goes high when the system is in minimum system voltage regulation.
To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configured by BATFET_DLY bit.
When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following events can enable BATFET to restore system power:
The PG_STAT bit goes HIGH and PG pin goes LOW to indicate a good input source when:
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin function can be disabled by setting the EN_ICHG_MON bits = 11.
CHARGING STATE | STAT INDICATOR |
---|---|
Charging in progress (including recharge) | LOW |
Charging complete | HIGH |
Sleep mode, charge disable | HIGH |
Charge suspend (input overvoltage, TS fault, timer fault or system overvoltage) |
Blinking at 1 Hz |
In some applications, the host does not always monitor the charger operation. The INT pulse notifies the system on the device operation. The following events will generate 256-μs INT pulse.
When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send any INT upon new faults. To read the current fault status, the host has to read REG09 two times consecutively. The first read reports the pre-existing fault register status and the second read reports the current fault register status.
The device closely monitors the input and system voltage, as well as internal FET currents for safe buck mode operation.
This device integrates the functionality of an overvoltage protector. The input voltage is sensed via the VAC pin. The OVP threshold defaults to 6.2V, but can be programmed at 5.5V, 6.2V, 10.5V, or 14.3V via OVP register bits. The ACOV circuit has a reaction time of tAC_OV_FLT.
During input overvoltage event (ACOV), the fault register CHRG_FAULT bits are set to 01. An INT pulse is asserted to the host. The device will automatically resume normal operation once the input voltage drops back below the OVP threshold.
The bq25600C device monitors the internal junction temperature TJ to avoid overheat the chip and limits the device surface temperature in buck mode. When the internal junction temperature exceeds thermal regulation limit (110°C), the device lowers down the charge current. During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when device surface temperature exceeds TSHUT(160ºC). The fault register CHRG_FAULT is set to 1 and an INT is asserted to the host. The BATFET and converter is enabled to recover when IC temperature is TSHUT_HYS (30ºC) below TSHUT(160ºC).
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charging. The fault register BAT_FAULT bit goes high and an INT is asserted to the host.
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 6AH, receiving control inputs from the master device like micro controller or a digital signal processor through REG00-REG0B. Register read beyond REG0B (0x0B) returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the mAster. The bus is considered busy after the START condition, and free after the STOP condition.
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the mAster into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge ninth clock pulse, are generated by the mAster. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The mAster can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
The charger device supports multi-read and multi-write on REG00 through REG0B.
REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. in order to get the fault information at present, the host has to read REG09 for the second time. The only exception is NTC_FAULT which always reports the actual condition on the TS pin. in addition, REG09 does not support multi-read and multi-write.
I2C Slave Address: 6AH
Bit | Field | POR | Type | Reset | Description | Comment |
---|---|---|---|---|---|---|
7 | EN_HIZ | 0 | R/W | by REG_RST by Watchdog |
0 – Disable, 1 – Enable | Enable HIZ Mode 0 – Disable (default) 1 – Enable |
6 | Reserved | |||||
5 | Reserved | |||||
4 | IINDPM[4] | 1 | R/W | by REG_RST | 1600 mA | Input Current Limit Offset: 100 mA Range: 100 mA (000000) – 3.2 A (11111) Default:, maximum input current limit, not typical. IINDPM bits are changed automatically after input source detection is completed bq25600C PSEL = Hi = 500 mA PSEL = Lo = Host can over-write IINDPM register bits after input source detection is completed. |
3 | IINDPM[3] | 0 | R/W | by REG_RST | 800 mA | |
2 | IINDPM[2] | 1 | R/W | by REG_RST | 400 mA | |
1 | IINDPM[1] | 1 | R/W | by REG_RST | 200 mA | |
0 | IINDPM[0] | 1 | R/W | by REG_RST | 100 mA |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description | Comment |
---|---|---|---|---|---|---|
7 | PFM _DIS | 0 | R/W | by REG_RST | 0 – Enable PFM 1 – Disable PFM |
Default: 0 - Enable |
6 | WD_RST | 0 | R/W | by REG_RST by Watchdog |
I2C Watchdog Timer Reset 0 – Normal ; 1 – Reset | Default: Normal (0) Back to 0 after watchdog timer reset |
5 | Reserved | |||||
4 | CHG_CONFIG | 1 | R/W | by REG_RST by Watchdog |
0 - Charge Disable 1- Charge Enable |
Default: Charge Battery (1) Note: 1. Charge is enabled when both CE pin is pulled low AND CHG_CONFIG bit is 1. |
3 | SYS_Min[2] | 1 | R/W | by REG_RST | System Minimum Voltage |
000: 2.6 V 001: 2.8 V 010: 3 V 011: 3.2 V 100: 3.4 V 101: 3.5 V 110: 3.6 V 111: 3.7 V Default: 3.5 V (101) |
2 | SYS_Min[1] | 0 | R/W | by REG_RST | ||
1 | SYS_Min[0] | 1 | R/W | by REG_RST | ||
0 | Reserved |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description | Comment |
---|---|---|---|---|---|---|
7 | Reserved | |||||
6 | Q1_FULLON | 0 | R/W | by REG_RST | 0 – Use higher Q1 RDSON when programmed IINDPM < 700mA (better accuracy) 1 – Use lower Q1 RDSON always (better efficiency) |
|
5 | ICHG[5] | R/W | by REG_RST by Watchdog |
Fast Charge Current Default: 2040mA (100010) Range: 0 mA (0000000) – 3000 mA (110010) Note: ICHG = 0 mA disables charge. ICHG > 3000 mA (110010 clamped to register value 3000 mA (110010)) |
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4 | ICHG[4] | 0 | R/W | by REG_RST by Watchdog |
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3 | ICHG[3] | R/W | by REG_RST by Watchdog |
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2 | ICHG[2] | R/W | by REG_RST by Watchdog |
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1 | ICHG[1] | 1 | R/W | by REG_RST by Watchdog |
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0 | ICHG[0] | R/W | by REG_RST by Watchdog |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description | Comment |
---|---|---|---|---|---|---|
7 | IPRECHG[3] | 0 | R/W | by REG_RST by Watchdog |
Precharge Current Default: 180 mA (0010) Offset: 60 mA Note: IPRECHG > clamped to (1100) |
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6 | IPRECHG[2] | 0 | R/W | by REG_RST by Watchdog |
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5 | IPRECHG[1] | R/W | by REG_RST by Watchdog |
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4 | IPRECHG[0] | R/W | by REG_RST by Watchdog |
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3 | ITERM[3] | 0 | R/W | by REG_RST by Watchdog |
Termination Current Default: 180 mA (0010) Offset: 60 mA Note: ITERM > 780 mA clamped to (1100) |
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2 | ITERM[2] | 0 | R/W | by REG_RST by Watchdog |
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1 | ITERM[1] | R/W | by REG_RST by Watchdog |
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0 | ITERM[0] | R/W | by REG_RST by Watchdog |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description | Comment |
---|---|---|---|---|---|---|
7 | VREG[4] | 0 | R/W | by REG_RST by Watchdog |
512 mV |
Charge Voltage Offset: 3.856 V Range: 3.856 V to 4.624 V (11000) Default: 4.208 V (01011) Special Value: (01111): 4.352 V Note: Value above 11000 (4.624 V) is clamped to register value 11000 (4.624 V) |
6 | VREG[3] | 1 | R/W | by REG_RST by Watchdog |
256 mV | |
5 | VREG[2] | 0 | R/W | by REG_RST by Watchdog |
128 mV | |
4 | VREG[1] | 1 | R/W | by REG_RST by Watchdog |
64 mV | |
3 | VREG[0] | 1 | R/W | by REG_RST by Watchdog |
32 mV | |
2 | Reserved | |||||
1 | Reserved | |||||
0 | VRECHG | 0 | R/W | by REG_RST by Watchdog |
0 – 100 mV 1 – 200 mV |
Recharge threshold Default: 100mV (0) |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description | Comment |
---|---|---|---|---|---|---|
7 | EN_TERM | 1 | R/W | by REG_RST by Watchdog |
0 – Disable 1 – Enable |
Default: Enable termination (1) |
6 | OVPFET_DIS | 0 | R/W | by REG_RST by Watchdog |
0 – Enable OVPFET 1 – Disable OVPFET |
Default: Enable OVPFET (0) Note: This bit only takes effect when EN_HIZ bit is active |
5 | WATCHDOG[1] | 0 | R/W | by REG_RST by Watchdog |
00 – Disable timer, 01 – 40 s, 10 – 80 s,11 – 160 s | Default: 40 s (01) |
4 | WATCHDOG[0] | 1 | R/W | by REG_RST by Watchdog |
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3 | EN_TIMER | 1 | R/W | by REG_RST by Watchdog |
0 – Disable 1 – Enable both fast charge and precharge timer |
Default: Enable (1) |
2 | CHG_TIMER | 1 | R/W | by REG_RST by Watchdog |
0 – 5 hrs 1 – 10 hrs |
Default: 10 hours (1) |
1 | TREG | 1 | R/W | by REG_RST by Watchdog |
Thermal Regulation Threshold: 0 - 90°C 1 - 110°C |
Default: 110°C (1) |
0 | Reserved |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description | Comment |
---|---|---|---|---|---|---|
7 | OVP[1] | 0 | R/W | by REG_RST | Default: 6.5V (01) | VAC OVP threshold: 00 - 5.5 V 01 – 6.5 V (5-V input) 10 – 10.5 V (9-V input) 11 – 14 V (12-V input) |
6 | OVP[0] | 1 | R/W | by REG_RST | ||
5 | Reserved | |||||
4 | Reserved | |||||
3 | VINDPM[3] | 0 | R/W | by REG_RST | 800 mV | Absolute VINDPM Threshold Offset: 3.9 V Range: 3.9 V (0000) – 5.4 V (1111) Default: 4.5V (0110) |
2 | VINDPM[2] | 1 | R/W | by REG_RST | 400 mV | |
1 | VINDPM[1] | 1 | R/W | by REG_RST | 200 mV | |
0 | VINDPM[0] | 0 | R/W | by REG_RST | 100 mV |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description | Comment |
---|---|---|---|---|---|---|
7 | Reserved | |||||
6 | TMR2X_EN | 1 | R/W | by REG_RST by Watchdog |
0 – Disable 1 – Safety timer slowed by 2X during input DPM (both V and I) or thermal regulation |
|
5 | BATFET_DIS | 0 | R/W | by REG_RST | 0 – Allow Q4 turn on, 1 – Turn off Q4 with tBATFET_DLY delay time (REG07[3]) | Default: Allow Q4 turn on(0) |
4 | Reserved | |||||
3 | BATFET_DLY | 1 | R/W | by REG_RST | 0 – Turn off BATFET immediately when BATFET_DIS bit is set 1 –Turn off BATFET after tBATFET_DLY (typ. 10 s) when BATFET_DIS bit is set |
Default: 1 Turn off BATFET after tBATFET_DLY (typ. 10 s) when BATFET_DIS bit is set |
2 | BATFET_RST_EN | 1 | R/W | by REG_RST by Watchdog |
0 – Disable BATFET reset function 1 – Enable BATFET reset function |
Default: 1 Enable BATFET reset function |
1 | VDPM_BAT_TRACK[1] | 0 | R/W | by REG_RST | 00 - Disable function (VINDPM set by register) 01 - VBAT + 200mV 10 - VBAT + 250mV 11 - VBAT + 300mV |
Sets VINDPM to track BAT voltage. Actual VINDPM is higher of register value and VBAT + VDPM_BAT_TRACK |
0 | VDPM_BAT_TRACK[0] | 0 | R/W | by REG_RST |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description |
---|---|---|---|---|---|
7 | VBUS_STAT[2] | x | R | NA | VBUS Status register bq25600C 000: No input 001: USB Host SDP (500 mA) → PSEL HIGH 010: Adapter → PSEL LOW 111: Reserved Software current limit is reported in IINDPM register |
6 | VBUS_STAT[1] | x | R | NA | |
5 | VBUS_STAT[0] | x | R | NA | |
4 | CHRG_STAT[1] | x | R | NA | Charging status: 00 – Not Charging 01 – Pre-charge (< VBATLOWV) 10 – Fast Charging 11 – Charge Termination |
3 | CHRG_STAT[0] | x | R | NA | |
2 | PG_STAT | x | R | NA | Power Good status: 0 – Power Not Good 1 – Power Good |
1 | THERM_STAT | x | R | NA | 0 – Not in ther mAl regulation 1 – in ther mAl regulation |
0 | VSYS_STAT | x | R | NA | 0 – Not in VSYSMin regulation (BAT > VSYSMin) 1 – in VSYSMin regulation (BAT < VSYSMin) |
LEGEND: R/W = Read/Write |
Bit | Field | POR | Type | Reset | Description |
---|---|---|---|---|---|
7 | WATCHDOG_FAULT | x | R | NA | 0 – Normal, 1- Watchdog timer expiration |
6 | Reserved | ||||
5 | CHRG_FAULT[1] | x | R | NA | 00 – Normal, 01 – input fault (VAC OVP or VBAT < VBUS < 3.8 V), 10 - Thermal shutdown, 11 – Charge Safety Timer Expiration |
4 | CHRG_FAULT[0] | x | R | NA | |
3 | BAT_FAULT | x | R | NA | 0 – Normal, 1 – BATOVP |
2 | Reserved | ||||
1 | Reserved | ||||
0 | Reserved |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description |
---|---|---|---|---|---|
7 | VBUS_GD | x | R | NA | 0 – Not VBUS attached, 1 – VBUS Attached |
6 | VINDPM_STAT | x | R | NA | 0 – Not in VINDPM, 1 – in VINDPM |
5 | IINDPM_STAT | x | R | NA | 0 – Not in IINDPM, 1 – in IINDPM |
4 | Reserved | x | R | NA | |
3 | Reserved | ||||
2 | ACOV_STAT | x | R | NA | 0 – Device is NOT in ACOV 1 – Device is in ACOV |
1 | VINDPM_INT_ MASK | 0 | R/W | by REG_RST | 0 - Allow VINDPM INT pulse 1 - Mask VINDPM INT pulse |
0 | IINDPM_INT_ MASK | 0 | R/W | by REG_RST | 0 - Allow IINDPM INT pulse 1 - Mask IINDPM INT pulse |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | POR | Type | Reset | Description |
---|---|---|---|---|---|
7 | REG_RST | 0 | R/W | NA | Register reset 0 – Keep current register setting 1 – Reset to default register value and reset safety timer Note: Bit resets to 0 after register reset is completed |
6 | PN[3] | x | R | NA | bq25600C: 0110 |
5 | PN[2] | x | R | NA | |
4 | PN[1] | x | R | NA | |
3 | PN[0] | x | R | NA | |
2 | Reserved | ||||
1 | DEV_REV[1] | x | R | NA | |
0 | DEV_REV[0] | x | R | NA |
LEGEND: R/W = Read/Write; R = Read only |