ZHCSJ79C December   2018  – January 2022 AWR1843

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions - Digital
      2. 7.2.2 Signal Descriptions - Analog
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Power Supply Sequencing and Reset Timing
      2. 8.10.2  Input Clocks and Oscillators
        1. 8.10.2.1 Clock Specifications
      3. 8.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.3.1 Peripheral Description
        2. 8.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.3.2.1 SPI Timing Conditions
          2. 8.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.10.3.3 SPI Peripheral Mode I/O Timings
          1. 8.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 8.10.4  LVDS Interface Configuration
        1. 8.10.4.1 LVDS Interface Timings
      5. 8.10.5  General-Purpose Input/Output
        1. 8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 8.10.6  Controller Area Network Interface (DCAN)
        1. 8.10.6.1 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 8.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 8.10.8  Serial Communication Interface (SCI)
        1. 8.10.8.1 SCI Timing Requirements
      9. 8.10.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.10.9.1 I2C Timing Requirements (1)
      10. 8.10.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.10.10.1 QSPI Timing Conditions
        2. 8.10.10.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.10.10.3 QSPI Switching Characteristics
      11. 8.10.11 ETM Trace Interface
        1. 8.10.11.1 ETMTRACE Timing Conditions
        2. 8.10.11.2 ETM TRACE Switching Characteristics
      12. 8.10.12 Data Modification Module (DMM)
        1. 8.10.12.1 DMM Timing Requirements
      13. 8.10.13 JTAG Interface
        1. 8.10.13.1 JTAG Timing Conditions
        2. 8.10.13.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.13.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Automotive Interface
      4. 9.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 9.3.5 DSP Subsystem Memory Map
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Short- and Medium-Range Radar
    3. 11.3 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABL|161
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.5 Power Supply Specifications

Table 8-1 describes the four rails from an external power supply block of the AWR1843 device.

Table 8-1 Power Supply Rails Characteristics
SUPPLY DEVICE BLOCKS POWERED FROM THE SUPPLY RELEVANT IOS IN THE DEVICE
1.8 V Synthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC, LVDS Input: VIN_18VCO, VIN18CLK, VIN_18BB, VIOIN_18DIFF, VIOIN_18
LDO Output: VOUT_14SYNTH, VOUT_14APLL
1.3 V (or 1 V in internal LDO bypass mode)(1) Power Amplifier, Low Noise Amplifier, Mixers and LO Distribution Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V I/O mode) Digital I/Os Input VIOIN
1.2 V Core Digital and SRAMs Input: VDDIN, VIN_SRAM
(1) Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply needs to be fed on the VOUT PA pin.

The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in Table 8-2 are defined to meet a target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted are rms levels for a sinusoidal input applied at the specified frequency.

Table 8-2 Ripple Specifications
FREQUENCY (kHz) RF RAIL VCO/IF RAIL
1.0 V (INTERNAL LDO BYPASS) (µVRMS) 1.3 V (µVRMS) 1.8 V (µVRMS)
137.5 7 648 83
275 5 76 21
550 3 22 11
1100 2 4 6
2200 11 82 13
4400 13 93 19
6600 22 117 29