ZHCSD06 November   2014 ADS58J89

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: 250 MSPS Output, 2x Decimation Filter
    7. 6.7  Electrical Characteristics: 500 MSPS Output
    8. 6.8  Electrical Characteristics: Sample Clock Timing Characteristics
    9. 6.9  Electrical Characteristics: Digital Outputs
    10. 6.10 Timing Requirements
    11. 6.11 Reset Timing
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Decimation by 2 (250 MSPS Output)
      2. 7.3.2  Over-Range Indication
      3. 7.3.3  JESD204B Interface
        1. 7.3.3.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.3.3.2 JESD204B Test Patterns
        3. 7.3.3.3 JESD204B Frame Assembly
      4. 7.3.4  SYSREF Clocking Schemes
      5. 7.3.5  Split-Mode Operation
      6. 7.3.6  Eye Diagram Information
      7. 7.3.7  Analog Inputs
      8. 7.3.8  Clock Inputs
      9. 7.3.9  Input Clock Divider
      10. 7.3.10 Power-Down Control
      11. 7.3.11 Device Configuration
      12. 7.3.12 JESD204B Interface Initialization Sequence
      13. 7.3.13 Device and Register Initialization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Mode Configuration
      3. 7.4.3 Output Format
      4. 7.4.4 Burst Mode of Every Other Sample (250 MSPS Output)
      5. 7.4.5 SNR Boost (500 MSPS Output)
      6. 7.4.6 Burst Mode
        1. 7.4.6.1 Burst Mode Counters
        2. 7.4.6.2 Burst Mode
        3. 7.4.6.3 TDD Burst Mode
        4. 7.4.6.4 Trigger Input
        5. 7.4.6.5 Manual Trigger Mode
        6. 7.4.6.6 Auto Trigger Mode
        7. 7.4.6.7 TDD-Burst Mode
          1. 7.4.6.7.1 TDD Burst Mode Examples
    5. 7.5 Programming
      1. 7.5.1 Serial Register Write
      2. 7.5.2 Serial Register Readout
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  Register Address 0
        2. 7.6.1.2  Register Address 1
        3. 7.6.1.3  Register Address 2
        4. 7.6.1.4  Register Address 3
        5. 7.6.1.5  Register Address 4
        6. 7.6.1.6  Register Address 5
        7. 7.6.1.7  Register Address 6
        8. 7.6.1.8  Register Address 7
        9. 7.6.1.9  Register Address 8
        10. 7.6.1.10 Register Address 12
        11. 7.6.1.11 Register Address 13
        12. 7.6.1.12 Register Address 14
        13. 7.6.1.13 Register Address 15
        14. 7.6.1.14 Register Address 16
        15. 7.6.1.15 Register Address 19
        16. 7.6.1.16 Register Address 22
        17. 7.6.1.17 Register Address 23
        18. 7.6.1.18 Register Address 26
        19. 7.6.1.19 Register Address 29
        20. 7.6.1.20 Register Address 30
        21. 7.6.1.21 Register Address 31
        22. 7.6.1.22 Register Address 32
        23. 7.6.1.23 Register Address 33
        24. 7.6.1.24 Address: 0x24, 0x25, 0x26, 0x27
        25. 7.6.1.25 Address: 0x28, 0x29, 0x2A, 0x2B
        26. 7.6.1.26 Register Address 44
        27. 7.6.1.27 Register Address 45
        28. 7.6.1.28 Register Address 46
        29. 7.6.1.29 Register Address 47
        30. 7.6.1.30 Address: 0x32, 0x33, 0x34, 0x35
        31. 7.6.1.31 Address: 0x36, 0x37, 0x38, 0x39
        32. 7.6.1.32 Register Address 58
        33. 7.6.1.33 Register Address 59
        34. 7.6.1.34 Register Address 60
        35. 7.6.1.35 Register Address 61
        36. 7.6.1.36 Register Address 99
        37. 7.6.1.37 Register Address 100
        38. 7.6.1.38 Register Address 103
        39. 7.6.1.39 Register Address 104
        40. 7.6.1.40 Register Address 107
        41. 7.6.1.41 Register Address 108
        42. 7.6.1.42 Register Address 111
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SNR and Clock Jitter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML SerDes Transmitter Interface
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

The Device EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in . Some important points to remember during laying out the board are:

  • Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package level. To minimize crosstalk on-board, the analog inputs should exit the pinout in opposite directions, as shown in the reference layout of as much as possible.
  • In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of as much as possible.
  • Digital outputs should be kept away from the analog inputs. When these digital outputs exit the pinout, the digital output traces should not be kept parallel to the analog input traces because this configuration may result in coupling from digital outputs to analog inputs and degrade performance. The digital sample data rate can be as high as 5.0 Gsps, so care must be taken to maintain the signal integrity of these signals. A low-loss dielectric circuit board is recommended or else these traces should be kept as short as possible. These traces should be kept away from the analog inputs ad n clock input to the device as well.
  • At each power-supply pin (AVDD, DRVDD, or AVDDD3V), a 0.1-μF decoupling capacitor should be kept close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-μF,
    1-μF, and 0.1-μF capacitors can be kept close to the supply source.

10.1.1 CML SerDes Transmitter Interface

Each of the 5 Gbps SerDes CML transmitter outputs requires AC coupling between transmitter and receiver. The differential pair should be terminated with a 100-Ω resistor as close to the receiving device as possible to avoid unwanted reflections and signal degradation.

10.2 Layout Example

CML_Serdes_int_BAS659.gifFigure 112. Layout Example Schematic
layout_BAS659.pngFigure 113. Top and Bottom Layers