ZHCSAM3B December 2012 – April 2022 ADS54T01
PRODUCTION DATA
After power up, TI recommends to initialize the device through a hardware reset by applying a logic low pulse on the SRESETb pin (of width greater than 20 ns), as shown in Figure 8-19. This resets all internal digital blocks (including SPI registers) to their default condition.
Figure 8-19 Device Initialization Timing Diagram| PARAMETER | CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| t1 | Power-on delay | Delay from power up to active low RESET pulse | 3 | ms | ||
| t2 | Reset pulse width | Active low RESET pulse width | 20 | ns | ||
| t3 | Register write delay | Delay from RESET disable to SDENb active | 100 | ns | ||
Recommended Device Initialization Sequence: