ZHCS190D May   2011  – November 2015 ADS5263

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, Dynamic Performance - 16-Bit ADC
    6. 7.6  Electrical Characteristics, General - 16-Bit ADC Mode
    7. 7.7  Electrical Characteristics, Dynamic Performance - 14-Bit ADC
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 LVDS Timing at Lower Sampling Frequencies - 2 Wire, 8× Serialization
    11. 7.11 LVDS Timing for 1 Wire 16× Serialization
    12. 7.12 LVDS Timing for 2 Wire, 7× Serialization
    13. 7.13 LVDS Timing for 1 Wire, 14× Serialization
    14. 7.14 Serial Interface Timing Requirements
    15. 7.15 Reset Switching Characteristics
    16. 7.16 Typical Characteristics
      1. 7.16.1 Typical Characteristic - 16-Bit ADC Mode
      2. 7.16.2 Typical Characteristic - 14-Bit ADC Mode
      3. 7.16.3 Typical Characteristics - Common Plots
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Processing Blocks
      2. 8.3.2 Digital Gain
      3. 8.3.3 Digital Filter
      4. 8.3.4 Custom Filter Coefficients
        1. 8.3.4.1 Custom Filter Without Decimation
      5. 8.3.5 Digital Averaging
      6. 8.3.6 Performance with Digital Processing Blocks
        1. 8.3.6.1 18-Bit Data Output with Digital Processing
      7. 8.3.7 Flexible Mapping o Channel Data to LVDS Outputs
      8. 8.3.8 Output LVDS Interface
      9. 8.3.9 Programmable LCLK Phase
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 Serial Register Readout
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Register Initialization
    6. 8.6 Register Maps
      1. 8.6.1 Default State After Reset
      2. 8.6.2 Description of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
        1. 9.1.1.1 Drive Circuit Requirements
      2. 9.1.2 Large and Small Signal Input Bandwidth
      3. 9.1.3 Clamp Function For CCD Signals
        1. 9.1.3.1 Differential Input Drive
        2. 9.1.3.2 Clamp Operation
        3. 9.1.3.3 Synchronization to External CCD Timing
      4. 9.1.4 Low-Frequency Noise Suppression
      5. 9.1.5 External Reference Mode
    2. 9.2 Typical Applications
      1. 9.2.1 Driving Circuit Design: Low Input Frequencies (< 50 MHz)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Driving Circuit Design: Input Frequencies > 50 MHz
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 技术规范定义
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息
    1. 13.1 封装
      1. 13.1.1 外露焊盘
      2. 13.1.2 非磁性封装

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • 最大采样率：100MSPS
  • 可编程器件分辨率
    • 四通道，16 位，高 SNR 模式
    • 四通道，14 位，低功耗模式
  • 16 位高 SNR 模式
    • 100MSPS 时总体功耗为 1.4W
      • 每通道 355mW
    • 4 Vpp 满量程输入
    • f输入= 3MHz，100MSPS 时，85dBFS SNR
  • 14 位低功耗模式
    • 100MSPS 下总体功耗 785mW
      • 每通道 195mW
    • 2 Vpp 满量程输入
    • f输入= 10MHz，74dBFS SNR
    • 集成钳位（用于与电荷耦合元件 (CCD) 传感器对接）
  • 低频噪声抑制
  • 数字处理块
    • 可编程 FIR 抽取滤波器
    • 可编程数字增益：0dB 至 12dB
    • 平均 2 或 4 通道
  • ADC 输入通道与低压差分信令 (LVDS) 输出引脚间的可编程映射 - 简化了电路板设计
  • 多种测试模式以验证现场可编程栅极阵列 (FPGA) /接收器的数据捕捉
  • 已串化 LVDS 输出
  • 内部和外部基准
  • 3.3V 模拟电源
  • 1.8V 数字电源
  • 在 1 个时钟周期内从 6dB 过载内恢复
  • 封装：
    • 9mm × 9mm 64 引脚四方扁平无引线 (QFN)
    • 针对磁共振成像 (MRI) 系统的非磁性封装选项
  • CMOS 技术

2 应用

  • 医疗成像 - MRI
  • 光谱分析
  • CCD 成像

3 说明

通过使用 CMOS 工艺技术和创新型电路技术，ADS5263 被设计用来在低功耗下运行，并且在 4 Vpp 满量程输入时提供极高的 SNR 性能。通过使用一个低噪声 16 位模拟前端级，之后是一个 14 位 ADC，此器件提供高达 10MHz 的 85dBFS SNR，以及高达 30MHz，优于 80dBFS 的 SNR。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
ADS5263 VQFN (64) 9.00mm x 9.00mm
  1. 要了解所有可用封装，请见数据表末尾的可订购产品附录。

ADS5263 框图

ADS5263 FBD_SLAS760.gif

4 修订历史记录

Changes from C Revision (January 2013) to D Revision

  • Added Register 57 in Register Maps Go
  • Added Register CB in Register Maps Go
  • Added Typical Applications sectionGo
  • Added Layout section Go
  • Deleted Ordering Information table. See POA at the end of the data sheet. Go

Changes from B Revision (October 2011) to C Revision

  • Changed Pin 54 From: REFB To: NCGo
  • Changed Pin 55 From: REFC To: NCGo
  • Changed the VCM Pin description To: "Internal reference mode: Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input External reference mode: Apply voltage input that sets the reference for ADC operation." From: "Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input pins."Go
  • Added "Idle channel noise" To SNRGo
  • Added "Idle channel noise" To LSBGo
  • Changed the INL values- 100 MSPS From: TYP = ±2.2 To: ±5, Added MAX = ±12Go
  • to Changed the INL values- 80 MSPS From: TYP = ±2.2 To: ±5Go
  • Added From: VCM common-mode output voltage To: VCM common-mode output voltage, Internal reference mode Go
  • Added From: VCM output current capability To: VCM output current capability, Internal reference modeGo
  • Added From: VCM input voltage To: VCM input current, external reference modeGo
  • Added VCM input current, external reference mode Typical value - 80 MSPS of 0.5Go
  • Changed EGREF - 100 MSPS MIN value From: ±2.5 To: ±1Go
  • Added Temperature Coefficient to EGREF Go
  • Added Temperature Coefficient to EGCHANGo
  • Changed SNR fin = 5 MHz MIN value From: 68.8 To: to 67.5Go
  • Added tA Aperture delay to the Timing Requirements TableGo
  • Changed From: 2 WIRE, 16× SERIALIZATION To: 2 WIRE, 8× SERIALIZATIONGo
  • Added 100 MSPS to the SAMPLING FREQUENCY, MSPS column of LVDS Timing at Lower Sampling Frequencies - 2 Wire, 8× SerializationGo
  • Changed to 8x from 16xGo
  • Changed LVDS Timing for 2 Wire, 7× Serialization title From: LVDS Timing for 2 Wire, 14× Serialization To: LVDS Timing for 2 Wire, 7× SerializationGo
  • Changed the Digital Filter SectionGo
  • Changed Table 9 Description From: Reference voltage must be forced on REFT and REFB pins To: Apply voltage on VCM pin to set the references for ADC operationGo
  • Table 10 Added: <EN_HIGH_ADDRS> as bit D4. Added: Register 0x09 to Serial Register Ma;Go
  • Table 10 Added: Register bit EXT_REF_VCM. Added: D12 <18x SERIALIZATION>Go
  • Table 10 Added: new register entries from Address 5A to 89. Added: new register F0Go
  • Added D4 <EN_HIGH_ADDRS>Go
  • Added Added register description table (D10 <EN_CLAMP>) for register 0x09Go
  • Added description for register EXT_REF_VCM Go
  • Added Description for <EN_REG_42>, <PHASE_DDR> and EXT_REF_VCMGo
  • Added Decsription for 18b SERIALIZATIONGo
  • Changed D11, D10, and D5 To: SERIALIZATION From: SERIAL'NGo
  • Changed the register for A7-A0 IN HEXGo
  • Added description for register F0 for A7–A0 IN HEXGo
  • Replaced the Clamp Function section with the Clamp Functon for CCD Signals sectionGo
  • Deleted Figure - CCD Sensor ConnectionsGo
  • Added External Reference ModeGo

Changes from A Revision (August 2011) to B Revision

  • Added new Figure below Figure 16Go
  • Added new Figure below Figure 22 (now Figure 24)Go
  • Added new section below Digital Averaging titled: Performance with Didgital Processing BlocksGo
  • Added listitem 6. to the OUTPUT LVDS INTERFACE sectionGo
  • Added Added new figure in section Output LVDS Interface (Figure 55)Go
  • Added new section after Output LVDS Interface titled: Programmable LCLK Phase, also 2 new figures added.Go
  • Added register 42 between register 38 and register 45 Go
  • Added new figure 52 in Large and Smll Signal Input Bandwidth sectionGo

Changes from * Revision (May 2011) to A Revision

  • 已添加“针对磁共振成像 (MRI) 系统的非磁性封装选项”至 特性Go
  • 已更改 特性 列表项 - 由“100MSPS 时的总功耗为 1.35W”改为“100MSPS 时的总功耗为 1.4W”Go
  • 已更改 特性 列表项 - 由“每通道 338mW”改为“每通道 355mW”Go
  • Changed the CLOCK INPUT values in the ROC tableGo
  • Changed the ELECTRICAL CHARACTERISTICS, DYNAMIC PERFORMANCE – 16-BIT ADC tableGo
  • Changed the ELECTRICAL CHARACTERISTICS, GENERAL – 16-BIT ADC MODE tableGo
  • Added the ELECTRICAL CHARACTERISTICS, DYNAMIC PERFORMANCE – 14-BIT ADC tableGo
  • Changed the values in DIGITAL OUTPUTS – LVDS INTERFACEGo
  • Added LVDS Timing for 1 Wire 16× Serialization, LVDS Timing for 2 Wire, 7× Serialization, and LVDS Timing for 1 Wire, 14× SerializationGo
  • Added Figure 25, Figure 26, and Figure 27Go
  • Added section - Large and Small Signal Input BandwidthGo
  • Added Section - Board Design ConsiderationsGo
  • Added Package Marking ADS5263NM and Ordering Number ADS5263IRGC-NMGo
  • 已添加“技术规范定义”部分Go
  • 已添加“封装”部分Go