4 修订历史记录

Changes from A Revision (May 2016) to B Revision

• 特性，将交流性能更改为：交流 + 直流性能Go
• 特性，将 SNR：最高可达 115.5dB（在 OSR 256 条件下）更改为：SNR：最高可达 115.5dBGo
• 特性，将 THD：–126dB（低功耗 (LP) 和超低功耗 (VLP) 模式）更改为：THD：低至 -129dBGo
• 特性，将直流精度更改为：积分非线性：1ppm Go
• 特性，将 HR：111dB SNR 更改为：高分辨率Go
• 特性，将 LP：108dB SNR 更改为：低功耗Go
• 特性，将 VLP：105dB SNR 更改为：超低功耗Go
• Pin Functions, Changed pin 14 description of 1: Master mode.Go
• Pin Functions, Changed pin 19 description "protocol" To: interfaceGo
• Pin Functions, Changed pin 27 description "Decouple DVDD to DGND with a 1-μF capacitor" To: Connect a 1-μF capacitor to DGNDGo
• Pin Functions, Changed pin 32 description "Decouple AVDD to AGND with a 1-μF capacitor" To: Connect a 1-μF capacitor to AGNDGo
• Recommended Operating Conditions, Changed V_CM NOM value From: (AVDD + AGND) / 2 To: AVDD / 2 Go
• Electrical Characteristics, Added test conditions to SNR: WB2, OSR 32/64/128, V_REF = 3 VGo
• Figure 2, Changed t_h(DO) To: t_v(DO) in order to match Switching Characteristics: Serial Interface Mode tableGo
• Timing Requirements: Frame-Sync Slave Mode, Deleted text from conditions statement "and DVDD = 1.7 V to 3.6 V"Go
• Typical Characteristics, Changed conditions statementGo
• Table 1, Changed the values in the ENOB columnGo
• Table 2, Changed the values in the ENOB columnGo
• Changed text frame-sync mode To: frame-sync interface mode throughout the documentGo
• Changed text frame-sync protocol. To: frame-sync interface mode throughout the documentGo
• Changed section Mode Selection To: Operating Modes (HR, LP, VLP)Go
• Changed section Filter Selection Pins (FILTER) To: Digital-Filter Path Selection Pins (FILTER[1:0])Go
• Figure 85, Changed t_w(STH) To: t_w(STL)Go
• Table 13, Changed t_w(STH) To: t_w(STL)Go
• Start Pin (START), Deleted text "For consistent performance, reassert START after device power-on when data first appear, or after any hardware MODE pin change."Go
• Figure 86, Changed t_w(STH) To: t_w(STL)Go
• Table 14, Changed t_w(STH) To: t_w(STL)Go
• Data Ready (DRDY/FSYNC), Changed "...with the first SCLK rising edge." To: "...with the first SCLK falling edge, as shown in Figure 91."Go
• Data Ready (DRDY/FSYNC), Added text "A new conversion result is..."Go
• Data Ready (DRDY/FSYNC), Added Figure 91Go
• START (0000 100x), Added sentence "The START command is decoded..." Go
• STOP (0000 101x), Added sentence "The START pin must be held low..."Go
• RREG (0010 rrrr 0000 nnnn), Added Figure 92Go
• WREG (0100 rrrr 0000 nnnn), Added Figure 93Go
• Synchronizing Devices, Added text "When synchronizing multiple devices..."Go
• Figure 112, Changed position of f_MOD arrowGo
• Antialiasing Filter, Changed paragraph following Figure 112 Go
• Table 30, Changed THS4551 Gain Bandwidth Product (MHz) From: 130 To: 135Go
• Modulator Saturation, Added new sectionGo
• Table 32, Changed values in the Noise columnGo
• Detailed Design Procedure, Changed "With a 130-MHz gain-bandwidth product" To: "With a 135-MHz gain-bandwidth product" Go
• Layout Guidelines, Changed sectionGo

Changes from * Revision (April 2016) to A Revision

• 已从“产品预览”更改为“量产数据”Go