ZHCSHA5E july   2010  – july 2023 ADS1013-Q1 , ADS1014-Q1 , ADS1015-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6.   Device Comparison Table
  7. 5 Pin Configuration and Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: I2C
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Multiplexer
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Full-Scale Range (FSR) and LSB Size
      4. 7.3.4 Voltage Reference
      5. 7.3.5 Oscillator
      6. 7.3.6 Output Data Rate and Conversion Time
      7. 7.3.7 Digital Comparator (ADS1014-Q1 and ADS1015-Q1 Only)
      8. 7.3.8 Conversion Ready Pin (ADS1014-Q1 and ADS1015-Q1 Only)
      9. 7.3.9 SMbus Alert Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power-Up
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Single-Shot Mode
        2. 7.4.2.2 Continuous-Conversion Mode
      3. 7.4.3 Duty Cycling For Low Power
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Address Selection
        2. 7.5.1.2 I2C General Call
        3. 7.5.1.3 I2C Speed Modes
      2. 7.5.2 Target Mode Operations
        1. 7.5.2.1 Receive Mode
        2. 7.5.2.2 Transmit Mode
      3. 7.5.3 Writing To and Reading From the Registers
      4. 7.5.4 Data Format
    6. 7.6 Register Map
      1. 7.6.1 Address Pointer Register (address = N/A) [reset = N/A]
      2. 7.6.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]
      3. 7.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]
      4. 7.6.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Connections
      2. 8.1.2 Single-Ended Inputs
      3. 8.1.3 Input Protection
      4. 8.1.4 Unused Inputs and Outputs
      5. 8.1.5 Analog Input Filtering
      6. 8.1.6 Connecting Multiple Devices
      7. 8.1.7 Quick-Start Guide
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Shunt Resistor Considerations
        2. 8.2.2.2 Operational Amplifier Considerations
        3. 8.2.2.3 ADC Input Common-Mode Considerations
        4. 8.2.2.4 Resistor (R1, R2, R3, R4) Considerations
        5. 8.2.2.5 Noise and Input Impedance Considerations
        6. 8.2.2.6 First-Order RC Filter Considerations
        7. 8.2.2.7 Circuit Implementation
        8. 8.2.2.8 Results Summary
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Sequencing
      2. 8.3.2 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  12. 10Mechanical, Packaging, and Orderable Information

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7.5.3 Writing To and Reading From the Registers

To access a specific register from the ADS101x-Q1, the controller must first write an appropriate value to register address pointer bits P[1:0] in the Address Pointer register. The Address Pointer register is written to directly after the target address byte, low R/W bit, and a successful target acknowledgment. After the Address Pointer register is written, the target acknowledges, and the controller issues a STOP or a repeated START condition.

When reading from the ADS101x-Q1, the previous value written to bits P[1:0] determines the register that is read. To change which register is read, a new value must be written to P[1:0]. To write a new value to P[1:0], the controller issues a target address byte with the R/W bit low, followed by the Address Pointer register byte. No additional data has to be transmitted, and a STOP condition can be issued by the controller. The controller can now issue a START condition and send the target address byte with the R/W bit high to begin the read. Figure 7-9 details this sequence. If repeated reads from the same register are desired, there is no need to continually send the Address Pointer register, because the ADS101x-Q1 store the value of P[1:0] until modified by a write operation. However, for every write operation, the Address Pointer register must be written with the appropriate values.

GUID-AD74B38F-687D-448F-AA98-85B00FDEAC67-low.gif
A. The values of A0 and A1 are determined by the ADDR pin.
B. The controller can leave SDA high to terminate a single-byte read operation.
C. The controller can leave SDA high to terminate a two-byte read operation.
Figure 7-9 Timing Diagram for Reading From ADS101x-Q1
GUID-F0AEA96C-7B80-406E-88C4-8223084AB63C-low.gif
A. The values of A0 and A1 are determined by the ADDR pin.
Figure 7-10 Timing Diagram for Writing to ADS101x-Q1
GUID-36BEE77F-132F-4E94-9170-5C04DA8C1A5F-low.gif
A. The values of A0 and A1 are determined by the ADDR pin.
Figure 7-11 Timing Diagram for SMBus Alert Response