ZHCSHA5E july   2010  – july 2023 ADS1013-Q1 , ADS1014-Q1 , ADS1015-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6.   Device Comparison Table
  7. 5 Pin Configuration and Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: I2C
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Multiplexer
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Full-Scale Range (FSR) and LSB Size
      4. 7.3.4 Voltage Reference
      5. 7.3.5 Oscillator
      6. 7.3.6 Output Data Rate and Conversion Time
      7. 7.3.7 Digital Comparator (ADS1014-Q1 and ADS1015-Q1 Only)
      8. 7.3.8 Conversion Ready Pin (ADS1014-Q1 and ADS1015-Q1 Only)
      9. 7.3.9 SMbus Alert Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power-Up
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Single-Shot Mode
        2. 7.4.2.2 Continuous-Conversion Mode
      3. 7.4.3 Duty Cycling For Low Power
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Address Selection
        2. 7.5.1.2 I2C General Call
        3. 7.5.1.3 I2C Speed Modes
      2. 7.5.2 Target Mode Operations
        1. 7.5.2.1 Receive Mode
        2. 7.5.2.2 Transmit Mode
      3. 7.5.3 Writing To and Reading From the Registers
      4. 7.5.4 Data Format
    6. 7.6 Register Map
      1. 7.6.1 Address Pointer Register (address = N/A) [reset = N/A]
      2. 7.6.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]
      3. 7.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]
      4. 7.6.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Connections
      2. 8.1.2 Single-Ended Inputs
      3. 8.1.3 Input Protection
      4. 8.1.4 Unused Inputs and Outputs
      5. 8.1.5 Analog Input Filtering
      6. 8.1.6 Connecting Multiple Devices
      7. 8.1.7 Quick-Start Guide
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Shunt Resistor Considerations
        2. 8.2.2.2 Operational Amplifier Considerations
        3. 8.2.2.3 ADC Input Common-Mode Considerations
        4. 8.2.2.4 Resistor (R1, R2, R3, R4) Considerations
        5. 8.2.2.5 Noise and Input Impedance Considerations
        6. 8.2.2.6 First-Order RC Filter Considerations
        7. 8.2.2.7 Circuit Implementation
        8. 8.2.2.8 Results Summary
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Sequencing
      2. 8.3.2 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  12. 10Mechanical, Packaging, and Orderable Information

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订购信息

7.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]

The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and comparator modes.

Figure 7-15 Config Register - ADS1013-Q1
15 14 13 12 11 10 9 8
OS RESERVED MODE
R/W-1b R/W-000010b R/W-1b
7 6 5 4 3 2 1 0
DR[2:0] RESERVED
R/W-100b R/W-00011b
Figure 7-16 Config Register - ADS1014-Q1
15 14 13 12 11 10 9 8
OS RESERVED PGA[2:0] MODE
R/W-1b R/W-000b R/W-010b R/W-1b
7 6 5 4 3 2 1 0
DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0]
R/W-100b R/W-0b R/W-0b R/W-0b R/W-11b
Figure 7-17 Config Register - ADS1015-Q1
15 14 13 12 11 10 9 8
OS MUX[2:0] PGA[2:0] MODE
R/W-1b R/W-000b R/W-010b R/W-1b
7 6 5 4 3 2 1 0
DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0]
R/W-100b R/W-0b R/W-0b R/W-0b R/W-11b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-6 Config Register Field Descriptions
Bit Field Type Reset Description
15 OS R/W 1b Operational status or single-shot conversion start
This bit determines the operational status of the device. OS can only be written when in power-down state and has no effect when a conversion is ongoing.


When writing:
0b : No effect
1b : Start a single conversion (when in power-down state)

When reading:
0b : Device is currently performing a conversion
1b : Device is not currently performing a conversion
14:12 MUX[2:0] R/W 000b Input multiplexer configuration (ADS1015-Q1 only)
These bits configure the input multiplexer.
These bits serve no function on the ADS1013-Q1 and ADS1014-Q1. ADS1013-Q1 and ADS1014-Q1 always use inputs AINP = AIN0 and AINN = AIN1.


000b : AINP = AIN0 and AINN = AIN1 (default)
001b : AINP = AIN0 and AINN = AIN3
010b : AINP = AIN1 and AINN = AIN3
011b : AINP = AIN2 and AINN = AIN3
100b : AINP = AIN0 and AINN = GND
101b : AINP = AIN1 and AINN = GND
110b : AINP = AIN2 and AINN = GND
111b : AINP = AIN3 and AINN = GND
11:9 PGA[2:0] R/W 010b Programmable gain amplifier configuration
These bits set the FSR of the programmable gain amplifier.
These bits serve no function on the ADS1013-Q1. ADS1013-Q1 always uses FSR = ±2.048 V.


000b : FSR = ±6.144 V(1)
001b : FSR = ±4.096 V(1)
010b : FSR = ±2.048 V (default)
011b : FSR = ±1.024 V
100b : FSR = ±0.512 V
101b : FSR = ±0.256 V
110b : FSR = ±0.256 V
111b : FSR = ±0.256 V
8 MODE R/W 1b Device operating mode
This bit controls the operating mode.


0b : Continuous-conversion mode
1b : Single-shot mode or power-down state (default)
7:5 DR[2:0] R/W 100b Data rate
These bits control the data rate setting.


000b : 128 SPS
001b : 250 SPS
010b : 490 SPS
011b : 920 SPS
100b : 1600 SPS (default)
101b : 2400 SPS
110b : 3300 SPS
111b : 3300 SPS
4 COMP_MODE R/W 0b Comparator mode (ADS1014-Q1 and ADS1015-Q1 only)
This bit configures the comparator operating mode.
This bit serves no function on the ADS1013-Q1.


0b : Traditional comparator (default)
1b : Window comparator
3 COMP_POL R/W 0b Comparator polarity (ADS1014-Q1 and ADS1015-Q1 only)
This bit controls the polarity of the ALERT/RDY pin.
This bit serves no function on the ADS1013-Q1.


0b : Active low (default)
1b : Active high
2 COMP_LAT R/W 0b Latching comparator (ADS1014-Q1 and ADS1015-Q1 only)
This bit controls whether the ALERT/RDY pin latches after being asserted or clears after conversions are within the margin of the upper and lower threshold values.
This bit serves no function on the ADS1013-Q1.


0b : Nonlatching comparator . The ALERT/RDY pin does not latch when asserted (default).
1b : Latching comparator. The asserted ALERT/RDY pin remains latched until conversion data are read by the controller or an appropriate SMBus alert response is sent by the controller. The device responds with an address, and is the lowest address currently asserting the ALERT/RDY bus line.
1:0 COMP_QUE[1:0] R/W 11b Comparator queue and disable (ADS1014-Q1 and ADS1015-Q1 only)
These bits perform two functions. When set to 11, the comparator is disabled and the ALERT/RDY pin is set to a high-impedance state. When set to any other value, the ALERT/RDY pin and the comparator function are enabled, and the set value determines the number of successive conversions exceeding the upper or lower threshold required before asserting the ALERT/RDY pin.
These bits serve no function on the ADS1013-Q1.


00b : Assert after one conversion
01b : Assert after two conversions
10b : Assert after four conversions
11b : Disable comparator and set ALERT/RDY pin to high-impedance (default)
(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to the analog inputs of the device.