ZHCSCD9C April   2014  – August 2014 ADC16DX370

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Performance Characteristics
    6. 6.6  Power Supply Electrical Characteristics
    7. 6.7  Analog Interface Electrical Characteristics
    8. 6.8  CLKIN, SYSREF, SYNCb Interface Electrical Characteristics
    9. 6.9  Serial Data Output Interface Electrical Characteristics
    10. 6.10 Digital Input Electrical Interface Characteristics
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Over-Range Functional Characteristics
    2. 7.2 Input Clock Divider and Clock Phase Adjustment Functional Characteristics
    3. 7.3 JESD204B Interface Functional Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Amplitude and Phase Imbalance Correction of Differential Analog Input
      2. 8.3.2  DC Offset Correction
      3. 8.3.3  Over-Range Detection
      4. 8.3.4  Input Clock Divider
      5. 8.3.5  SYSREF Offset Feature and Detection Gate
      6. 8.3.6  Sampling Instant Phase Adjustment
      7. 8.3.7  Serial Differential Output Drivers
        1. 8.3.7.1 De-Emphasis Equalization
      8. 8.3.8  ADC Core Calibration
      9. 8.3.9  Data Format
      10. 8.3.10 JESD204B Supported Features
      11. 8.3.11 Transport Layer Configuration
        1. 8.3.11.1 Lane Configuration
        2. 8.3.11.2 Frame Format
        3. 8.3.11.3 ILA Information
      12. 8.3.12 Test Pattern Sequences
      13. 8.3.13 JESD204B Link Initialization
      14. 8.3.14 SPI
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
    5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input Considerations
        1. 9.1.1.1 Differential Analog Inputs and Full Scale Range
        2. 9.1.1.2 Analog Input Network Model
        3. 9.1.1.3 Input Bandwidth
        4. 9.1.1.4 Driving the Analog Input
        5. 9.1.1.5 Clipping and Over-Range
      2. 9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 9.1.2.1 Driving the CLKIN+ and CLKIN- Input
        2. 9.1.2.2 Clock Noise and Edge Rate
        3. 9.1.2.3 Driving the SYSREF Input
        4. 9.1.2.4 SYSREF Signaling
        5. 9.1.2.5 SYSREF Timing
        6. 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
        7. 9.1.2.7 Driving the SYNCb Input
      3. 9.1.3 Output Serial Interface Considerations
        1. 9.1.3.1 Output Serial-Lane Interface
        2. 9.1.3.2 Voltage Swing and De-Emphasis Optimization
        3. 9.1.3.3 Minimizing EMI
      4. 9.1.4 JESD204B System Considerations
        1. 9.1.4.1 Frame and LMFC Clock Alignment Procedure
        2. 9.1.4.2 Link Interruption
        3. 9.1.4.3 Synchronization Requests and SYNCb Alignment in Multi-Device Systems
        4. 9.1.4.4 Clock Configuration Examples
        5. 9.1.4.5 Configuring the JESD204B Receiver
      5. 9.1.5 SPI
    2. 9.2 Typical Application
      1. 9.2.1 High-IF Sampling Receiver
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 技术规格定义
      2. 12.1.2 JESD204B 定义
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Detailed Description

8.1 Overview

The ADC16DX370 device is a dual analog-to-digital converter (ADC) composed of pipelined stages followed by a back-end JESD204B interface. Each ADC core is preceded by an input buffer and imbalance correction circuit at the analog input and is provided with the necessary reference voltages with internal drivers that require no external components. The analog input common-mode is also internally regulated.

Over-range signals are externally available on pins to monitor the signal path. A DC offset correction block is disabled by default, but may also be enabled at the ADC core output to remove DC offset. Processed data is passed into the JESD204B interface where the data is framed, encoded, serialized, and output on one or two lanes per channel. Data is serially transmitted by configurable high-speed voltage mode drivers.

The sampling clock is derived from the CLKIN input via a low-noise receiver and clock divider. Coarse delay adjustment blocks in the clock signal path control the phase of the sampling instant. The CLKIN, SYSREF, and SYNCb inputs provide the device clock, sysref, and sync~ signals to the JESD204B interface, which are used to derive the internal local frame and local multi-frame clocks and establish the serial link.

Features of the ADC16DX370 device are configurable through the 4-wire SPI.

8.2 Functional Block Diagram

ADC16DX370 Block_Diagram.gif

8.3 Feature Description

8.3.1 Amplitude and Phase Imbalance Correction of Differential Analog Input

The ADC performance can be sensitive to amplitude and phase imbalance of the input differential signal and therefore integrates a front-end balance correction circuit to optimize the second-order distortion (HD2) performance of the ADC in the presence of an imbalanced input signal. 4-bit control of the phase mismatch and 3-bit control of the amplitude mismatch corrects the input mismatch before the input buffer. A simplified diagram of the amplitude and phase correction circuit at the ADC input is shown in Figure 30.

ADC16DX370 ImbCorr_Circuit.gif Figure 30. Simplified Input Differential Balance Correction Circuit

Amplitude correction is achieved by varying the single-ended termination resistance of each input while maintaining constant total differential resistance, thereby adjusting the amplitude at each input but leaving the differential swing constant. Phase correction, also considered capacitive balance correction, varies the capacitive load at the ADC input, thereby correcting a phase imbalance by creating a bandwidth difference between the analog inputs that minimally affects amplitude. This function is useful for correcting the balance of transformers or filters that drive the ADC analog inputs. Figure 31 shows the measured HD2 resulting from an example 250-MHz imbalanced signal input into the ADC16DX370 device recorded over the available amplitude and phase correction settings, demonstrating the optimization of HD2. Performance parameters in the Converter Performance Characteristics are characterized with the amplitude and phase correction settings in the default condition.

ADC16DX370 HD2_ImbalanceCorrection.png Figure 31. Gain and Phase Imbalance HD2 Optimization at 250 MHz

8.3.2 DC Offset Correction

DC offset correction is provided using a digital high-pass IIR filter at the immediate output of the ADC core. The DC offset correction is bypassed by default, but may be enabled and configured via the SPI. The 3-dB bandwidth of the IIR digital correction filter may be set to four different low-frequency values. When DC offset correction is enabled, any signal in the stop-band of the high-pass filter is attenuated. The settling time of the DC offset correction is approximately equal to the inverse of the 3-dB bandwidth setting.

8.3.3 Over-Range Detection

Separate over-range detection output signals for channels A and B are dedicated to pins. The OVRA pin asserts (high) when an over-range signal is detected at the input of channel A. The short delay from when an over-range signal is incident at the input until the OVRA is asserted allows for almost immediate detection of over-range signals without delay from the internal ADC pipeline latency or data serialization latency. OVRB responds similarly when an over-range signal is detected at the input of channel B.

The input power threshold to indicate an over-range event is programmable via the SPI from full scale code range down to a ± 128 LSB code range in steps of 128 codes relative to the 16-bit code range of the data at the output of the ADC core.

After an over-range event occurs and the signal at the channel input reduces to a level below full-scale, an internal counter begins counting to provide a hold function. When the counter reaches a programmable counter threshold, the OVRA (or OVRB) signal is de-asserted. The duration of the hold counter is programmable via the SPI to hold for +3, +7, or +15 frame clock cycles. The counter is disabled (+0 cycles) by default to allow de-assertion without holding. Each channel has an independent hold counter but the hold duration value is common to both channels.

8.3.4 Input Clock Divider

An input clock divider allows a high frequency clock signal to be distributed throughout the system and locally divided down at the ADC device so that coupling of signals at common intermediate frequencies into other parts of the system can be avoided. The frequency at the CLKIN input may be divided down to the sampling rate of the ADC by factors of 1, 2, 4, or 8. Changing the clock divider setting initiates a JESD204 link re-initialization and requires re-calibration of the ADC if the sampling rate is changed from the rate during the previous calibration.

8.3.5 SYSREF Offset Feature and Detection Gate

When the signal at the SYSREF input is not actively toggling periodically, the SYSREF signal is considered to be in an idle state. The idle state is recommended at any time the ADC16DX370 spurious performance must be maximized. When the SYSREF signal is in the idle state for longer than 1 µs, an undesirable offset voltage may build up across the AC coupling capacitors between the SYSREF transmitter and the ADC16DX370 device input. This offset voltage creates a signal threshold problem, requires a long time to dissipate, and therefore prevents quick transition of the SYSREF signal out of the idle state. Two features are provided as a solution and are shown in Figure 48, namely the SYSREF offset feature and SYSREF detection gate.

In the case that the SYSREF signal idle state has a 0-V differential value, or if the ADC16DX370 device must be insensitive to noise that may appear on the SYSREF signal, then the SYSREF detection gate may be used. The detection gate is the AND gate shown in Figure 48 that enables or disables propagation of the SYSREF signal through to the internal device logic. If the detection gate is disabled and a false edge appears at the SYSREF input, the signal does not disrupt the internal clock alignment. Note that the SYSREF detection gate is disabled by default; therefore, the device does not respond to a SYSREF edge until the detection gate is enabled.

The SYSREF offset and detection gate features are both controlled through the SPI.

8.3.6 Sampling Instant Phase Adjustment

Adjustment of the ADC sampling instant relative to the CLKIN input clock may be controlled using the coarse phase adjustment feature.

Coarse clock phase adjustment is provided to control the phase of the sampling instant in the ADC cores. The coarse phase steps are equal to 1 / (2 × CLKDIV × FS) seconds over a 1 / FS second range where CLKDIV is the clock division factor and FS is the sampling rate. The coarse phase adjustment setting is common to both channels.

Affter the JESD204B serial link is established, the frame and LMFC clocks, as well as the internal reference clocks used by the JESD204B serializer, are not affected by the clock phase adjustments because the data is re-timed at the ADC core output. Changing the phase setting does not affect the status of the JESD204B link and does not cause glitches in the serial data. Varying the phase does not vary the timing of frames output on the JESD204B link, but it does vary the sampling instant relative to the internal frame clock. Therefore, the total latency from the sampling instant to the beginning of the frame output on the serial link changes equal to the change in the phase adjustment. This latency change is a fraction of a frame clock cycle.

The phase of the internal sampling clock is aligned to SYSREF events. This impacts the phase relationship between the input signal and sampling instant and may affect the latency across the link.

8.3.7 Serial Differential Output Drivers

The differential drivers of the ADC16DX370 device that output the serial JESD204B data are voltage mode drivers with amplitude control and de-emphasis features that may be configured through the SPI for a variety of different channel applications. Eight amplitude control (VOD) and eight de-emphasis control (DEM) settings are available. Both VOD and DEM register fields must be configured to optimize the noise performance of the serial interface for a particular lossy channel.

The output common-mode of the driver varies with the configuration of the output swing. Therefore, AC coupling is strongly recommended between the ADC16DX370 device and the device receiving the serial data.

8.3.7.1 De-Emphasis Equalization

De-emphasis of the differential output is provided as a form of continuous-time linear equalization that imposes a high-pass frequency response onto the output signal to compensate for frequency-dependent attenuation as the signal propagates through the channel to the receiver. In the time-domain, the de-emphasis appears as the bit transition transient followed by an immediate reduction in the differential amplitude, as shown in Figure 32. The characteristic appearance of the waveform changes with differential amplitude and the magnitude of de-emphasis applied. The serial lane rate determines the available period of time during which the de-emphasis transient settles. However, the lane rate does not affect the settling behavior of the applied de-emphasis.

ADC16DX370 Deemphasis_waveform.png Figure 32. De-emphasis of the Differential Output Signal

Table 1 indicates the typical measured values for the de-emphasis range, where the de-emphasis value is measured as the ratio (in units of [dB]) between the peak voltage after the signal transition to the settled voltage value in one bit period. The data rate for this measurement is 1.2 Gb/s to allow settling of the de-emphasis transient. Table 1 illustrates the actual de-emphasis value in terms of voltage attenuation and shows dependence on the amplitude setting, but does not reflect the optimal amplitude setting (VOD) and de-emphasis setting (DEM) for a particular lossy channel. Table 2 shows the amplitude of the differential signal swing during its settled state after the transition transient. The measurement is performed at 1.2 Gb/s and the units are in differential peak-to-peak mV.

Table 1. De-Emphasis Values (dB) for All VOD and DEM Configuration Settings

DEM
0 1 2 3 4 5 6 7
VOD 0 0 –0.4 –1.2 –2.1 –2.8 –3.8 –4.8 –6.8
1 0 –0.6 –1.7 –2.7 –3.5 –4.6 –5.7 –7.8
2 0 –0.8 –2.2 –3.3 –4.1 –5.3 –6.4 –8.6
3 0 –1.0 –2.6 –3.9 –4.7 –5.9 –7.0 –9.4
4 0 –1.3 –3.0 –4.3 –5.3 –6.5 –7.7 –9.9
5 0 –1.6 –3.5 –4.9 –5.8 –7.0 –8.3 –10.5
6 0 –1.9 –3.9 –5.3 –6.2 –7.5 –8.7 –11.0
7 0 –2.1 –4.2 –5.7 –6.7 –8.0 –9.3 –11.5

Table 2. Settled Differential Voltage Swing Values, VOD (peak-to-peak mV) for All VOD and DEM Configuration Settings

DEM
0 1 2 3 4 5 6 7
VOD 0 580 540 500 440 420 380 340 260
1 680 620 560 500 440 400 340 280
2 760 700 600 520 480 420 360 280
3 860 760 640 560 500 440 380 300
4 960 820 680 580 520 460 400 300
5 1060 880 700 600 540 460 400 320
6 1140 920 740 620 560 480 420 320
7 1240 960 760 640 580 500 420 320

8.3.8 ADC Core Calibration

The ADC core of this device requires calibration to be performed after power-up to achieve full performance. After power-up, the ADC16DX370 device detects that the supplies and clock are valid, waits for a power-up delay, and then performs a calibration of the ADC core automatically. The power-up delay is 8.4 × 106 sampling clock cycles or 22.7 ms at a 370-MSPS sampling rate. The calibration requires approximately 2.0 × 106 sampling clock cycles.

If the system requires that the ADC16DX370 input clock divider value (CLKDIV) is set to 2, 4, or 8, then ADC calibration must be performed manually after CLKDIV has been set to the desired value. Manually calibrating the ADC core is performed by changing to power down mode, returning to normal operation, and monitoring the CAL_DONE bit in the JESD_STATUS register until calibration is complete. As an alternative to monitoring CAL_DONE, the system may wait 2.5 × 106 sampling clock cycles until calibration completes.

Re-calibration is not required across the supported operating temperature range to maintain functional performance, but it is recommended for large changes in ambient temperature to maintain optimal dynamic performance. Changing the sampling rate always requires re-calibration of the ADC core. For more information about device modes, see Power-Down and Sleep Modes.

8.3.9 Data Format

Data may be output in the serial stream as 2’s complement format by default or optionally as offset binary. This formatting is configured through the SPI and is performed in the data path prior to JESD204B data framing and 8b/10b encoding.

8.3.10 JESD204B Supported Features

The ADC16DX370 device supports a feature set of the JESD204B standard targeted to its intended applications but does not implement all the flexibility of the standard. Table 3 summarizes the level of feature support.

Table 3. ADC16DX370 Feature Support for the JESD204B Serial Interface

Feature Supported Not Supported
Subclass
  • Subclass 1, 0(1)
  • Subclass 2
Device Clock
(CLKIN) and
SYSREF
  • AC coupled CLKIN and SYSREF
  • DC coupled CLKIN and SYSREF (special cases)
  • Periodic, Pulsed Periodic and One-Shot SYSREF
Latency
  • Deterministic latency supported for subclass 1 implementations using standard SYSREF signal
  • Deterministic latency not supported for non-standard implementations
Electrical layer features
  • LV-OIF-11G-SR interface and performance
  • AC coupled serial lanes
  • TX lane polarity inversion
  • DC coupled serial lanes
Transport layer features and configuration
  • L = 1 or 2 for each channel
  • K configuration
  • Scrambling
  • F, S, and HD configuration depends on L and is not independently configurable
  • M, N, N’, CS, CF configuration
  • Idle link mode
  • Short and Long transport layer test patterns
Data link layer features
  • 8b/10b encoding
  • Lane synchronization
  • D21.5, K28.5, ILA, PRBS7, PRBS23, Ramp test sequences
  • RPAT/JSPAT test sequences
(1) The ADC16DX370 supports most subclass 0 requirements, but is not strictly subclass compliant.

8.3.11 Transport Layer Configuration

The transport layer features supported by the ADC16DX370 device are a subset of possible features described in the JESD204B standard. The configuration options are intentionally simplified to provide the lowest power and most easy-to-use solution.

8.3.11.1 Lane Configuration

Each channel outputs its digital data on up to two serial lanes that support JESD204B. The number of transmission lanes per channel (L) is configurable as 1 or 2. The device does not allow transmitting both channels on the same lane. When using one serial lane per channel, the serial-data lane transmits at 20 times the sampling rate. A 370 MSPS sampling rate corresponds to a 7.4 Gb/s per lane rate. When using two serial lanes per channel, the serial data rate is 10 times the sampling rate. A 370 MSPS sampling rate corresponds to a 3.7 Gb/s per lane rate.

8.3.11.2 Frame Format

The format of the data arranged in a frame depends on the L setting. The octets per frame (F), samples per frame (S), and high-density mode (HD) parameters are not independently configurable. The N, N’, CS, CF, M, and HD parameters are fixed and not configurable. Figure 33 shows the data format for L = 1 and L = 2. M = 1 in this device, indicating one converter per device and each channel is considered a different device. Therefore, the L value corresponds to the number of lanes used by a channel, not the number of lanes output from the chip.

ADC16DX370 Data_Format.gif Figure 33. Transport Layer Definitions for the Supported-Lane Configurations

8.3.11.3 ILA Information

Table 4 summarizes the information transmitted during the initial lane alignment (ILA) sequence. Mapping of these parameters into the data stream is described in the JESD204B standard.

Table 4. Configuration of the JESD204B Serial-Data Receiver

Parameter Description Value
Single Lane Mode Dual Lane Mode
ADJCNT DAC LMFC adjustment 0 0
ADJDIR DAC LMFC adjustment direction 0 0
BID Bank ID 0 0
CF Number of control words per frame clock period per link 0 0
CS Number of control bits per sample 0 0
DID Device identification number 0 0
F Number of octets per frame (per lane)(1) 2 1
HD High-density format 0 1
JESDV JESD204 version 1 1
K Number of frames per multi-frame(1) Set by register as 9 to 32 Set by register as 17 to 32
L Number of lanes per link(1) 1 2
LID Lane identification number 0 0 (lane 0), 1 (lane 1)
M Number of converters per device(1) 1 1
N Converter resolution (1) 16 16
N’ Total number of bits per sample(1) 16 16
PHADJ Phase adjustment request to DAC 0 0
S Number of samples per converter per frame cycle(1) 1 1
SCR Scrambling enabled Set by register as 0 (disabled) or 1 Set by register as 0 (disabled) or 1
SUBCLASSV Device subclass version 1 1
RES1 Reserved field 1 0 0
RES2 Reserved field 2 0 0
FCHK Checksum Computed Computed
(1) These parameters have a binary-value-minus-1 encoding applied before being mapped into the link configuration octets. For example, F = 2 is encoded as 1, and F = 1 is encoded as 0.

Scrambling of the output serial data is supported and conforms to the JESD204B standard. Scrambling is disabled by default, but may be enabled via the SPI. When scrambling is enabled, the ADC16DX370 device supports the early synchronization option by the receiver during the ILA sequence, although the ILA sequence data is never scrambled.

8.3.12 Test Pattern Sequences

The SPI may enable the following test pattern sequences. Short- and long-transport layer, RPAT, and JSPAT sequences are not supported.

Table 5. Supported Test Pattern Sequences

Test Pattern Description Common Purpose
D21.5 Data is transmitted across a normal link but ADC sampled data is replaced with D21.5 symbols, resulting in an alternating 1 and 0 pattern (101010...) on each serial lane. After enabling this pattern, the JESD204B link must be reinitialized. Jitter or system debug
K28.5 Continuous K28.5 symbols are output on each serial lane. Link initialization is not possible nor required. System debug
Repeated ILA ILA repeats indefinitely on each serial lane. After enabling this pattern, the JESD204B link must be reinitialized. System debug
Ramp Data is transmitted across a normal link but ADC sampled data is replaced with a ramp pattern. The ramp ascends through a 16-bit range and the step is programmable. After enabling this pattern, the JESD204B link must be reinitialized. System debug and transport layer verification
PRBS Standard pseudo-random bit sequences are output on each serial lane. PRBS 7/15/23 Complies with ITU-T O.150 specification and is compatible with J-BERT equipment. Link initialization is not possible nor required. Jitter and bit error rate testing

8.3.13 JESD204B Link Initialization

A JESD204B link is established via link initialization, which involves the following steps: frame alignment, code group synchronization, and initial lane synchronization. These steps are shown in Figure 34. Link initialization must occur between the transmitting device (ADC16DX370) and receiving device before sampled data may be transmitted over the link. The link initialization steps described here are specifically for the ADC16DX370 device, supporting JESD204B subclass 1.

ADC16DX370 JESD204_Synchronization_Timing.gif Figure 34. Link-initialization Timing and Flow Diagram

The Frame Alignment step requires alignment of the frame and local multi-frame clocks within the ADC16DX370 device to an external reference. This is accomplished by providing the device clock and SYSREF clock to the CLKIN and SYSREF inputs, respectively. The ADC16DX370 device aligns its frame clock and LMFC to any SYSREF rising edge event, offset by a SYSREF-to-LMFC propagation delay.

The SYSREF signal must be source synchronous to the device clock; therefore, the SYSREF rising edge must meet setup and hold requirements relative to the signal at the CLKIN input. If these requirements cannot be met, then the alignment of the internal frame and multi-frame clocks cannot be specified. As a result, a link may still be established, but the latency through the link cannot be deterministic. Frame alignment may occur at any time; although, a re-alignment of the internal frame clock and LMFC will break the link. Note that frame alignment is not required for the ADC16DX370 device to establish a link because the device automatically generates the clocks on power-up with unknown phase alignment.

Code Group Synchronization is initiated when the receiver sends a synchronization request by asserting the SYNCb input of the ADC16DX370 device to a logic low state (SYNCb+ < SYNCb–). After the SYNCb assertion is detected, the ADC16DX370 device outputs K28.5 symbols on all serial lanes that are used by the receiver to synchronize and time align its clock and data recovery (CDR) block to the known symbols. The SYNCb signal must be asserted for at least 4 frame clock cycles otherwise the event is ignored by the ADC16DX370 device. Code group synchronization is completed when the receiver de-asserts the SYNCb signal to a logic high state.

After the ADC16DX370 detects a de-assertion of its SYNCb input, the Initial Lane Synchronization step begins on the following LMFC boundary. The ADC16DX370 device outputs 4 multi-frames of information that compose the ILA sequence. This sequence contains information about the data transmitted on the link. The initial lane synchronization step and link initialization conclude when the ILA is finished and immediately transitions into Data Transmission. During data transmission, valid sampled data is transmitted across the link until the link is broken.

ADC16DX370 JESD204_Sychronization_Flow_Chart.gif Figure 35. Device Start-Up and JESD204B Link Synchronization Flow Chart

The flowchart in Figure 35 describes how the ADC16DX370 device initializes the JESD204B link and reacts to changes in the link. After the ADC core calibration is finished, the ADC16DX370 device begins with PLL calibration and link initialization using a default frame clock and LMFC alignment by sending K28.5 characters. PLL calibration requires approximately 153×103 sampling clock cycles. If SYNCb is not asserted, then the device immediately advances to the ILA sequence at the next LMFC boundary. Whereas, if SYNCb is asserted, then the device continues to output K28.5 characters until SYNCb is de-asserted.

When a SYSREF rising edge event is detected, then the ADC16DX370 device compares the SYSREF event to the current alignment of the LMFC. If the SYSREF event is aligned to the current LMFC alignment, then no action is taken and the device continues to output data. If misalignment is detected, then the SYSREF event is compared to the frame clock. If misalignment of the frame clock is also detected, then the clocks are re-aligned and the link is reinitialized. If the frame clock is not misaligned, then the frame clock alignment is not updated. In the cases that a SYSREF event causes a link re-initialization, the ADC16DX370 device begins sending K28.5 characters without a SYNCb assertion and immediately transitions to the ILA sequence on the next LMFC boundary unless the SYNCb signal is asserted. Anytime the frame clock and LMFC are re-aligned, the serializer PLL must calibrate before code group synchronization begins. SYSREF events must not occur during ADC16DX370 device power-up, ADC calibration, or PLL calibration. The JESD_STATUS register is available to check the status of the ADC16DX370 device and the JESD204B link.

If a SYNCb assertion is detected for at least 4 frame clock cycles, the ADC16DX370 device immediately breaks the link and sends K28.5 characters until the SYNCb signal is de-asserted.

When exiting sleep mode, the frame clock and LMFC are started with a default (unknown) phase alignment, PLL calibration is performed, and the device immediately transitions into sending K28.5 characters.

8.3.14 SPI

The SPI allows access to the internal configuration registers of the ADC through read and write commands to a specific address. The interface protocol has a 1-bit command, 15-bit address word and 8-bit data word as shown in Figure 36. A read or write command is 24 bits in total, starting with the read or write command bit where 0 indicates a write command and 1 indicates a read command. The read or write command bit is clocked into the device on the first rising edge of SCLK after CSb is asserted to 0. During a write command, the 15-bit address and 8-bit data values follow the read or write bit MSB-first and are latched on the rising edge of SCLK. During a read command, the SDO output is enabled shortly after the 16th rising edge of SCLK and outputs the read value MSB first before the SDO output is returned to a high impedance state. The read or write command is completed on the SCLK rising edge on which the data word’s LSB is latched. CSb may be de-asserted to 1 after the LSB is latched into the device.

The SPI allows command streaming where multiple commands are made without de-asserting CSb in-between commands. The commands in the stream must be of similar types, either read or write. Each subsequent command applies to the register address adjacent to the register accessed in the previous command. The address order can be configured as either ascending or descending. Command streaming is accomplished by immediately following a completed command with another set of 8 rising edges of SCLK without de-asserting CSb. During a write command, an 8-bit data word is input on the SDI input for each subsequent set of SCLK edges. During a read command, data is output from SDO for each subsequent set of SCLK edges. Each subsequent command is considered finished after the 8th rising edge of SCLK. De-asserting CSb aborts an incomplete command.

The SDO output is high impedance at all times other than during the final portion of a read command. During the time that the SDO output is active, the logic level is determined by a configuration register. The SPI output logic level must be properly configured after power up and before making a read command to prevent damaging the receiving device or any other device connected to the SPI bus. Until the SPI_CFG register is properly configured, voltages on the SDO output may be as high as the VA3.0 supply during a read command. The SDI, SCLK, and CSB pins are all 1.2-V to 3.0-V compatible.

ADC16DX370 SPI_Protocol_Diagram.gif Figure 36. Serial Interface Protocol

8.4 Device Functional Modes

8.4.1 Power-Down and Sleep Modes

Power-down and sleep modes are provided to allow the user to reduce the power consumption of the device without disabling power supplies. Both modes reduce power consumption by the same amount but they differ in the amount of time required to return to normal operation. Upon changing from Power Down back to Normal operation, an ADC calibration routine is performed. Waking from sleep mode does not perform ADC calibration (see ADC Core Calibration for more details). Neither power-down mode nor sleep mode resets configuration registers.

8.5 Register Map

Table 6. ADC16DX370 Register Map

Register ADDRESS DFLT b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0]
CONFIG_A 0x0000 0x3C SR Res (0) ASCEND Res (1) PAL[3:0]
Address 0x0001 Reserved
DEVICE _CONFIG 0x0002 0x00 Reserved (000000) PD_MODE[1:0]
CHIP_TYPE 0x0003 0x03 Reserved (0000) CHIP_TYPE[3:0]
CHIP_ID 0x0004 0x02 CHIP_ID[7:0]
0x0005 0x00 CHIP_ID[15:8]
CHIP _VERSION 0x0006 0x01 CHIP_VERSION[7:0]
Address 0x0007-0x000B Reserved
VENDOR_ID 0x000C 0x51 VENDOR_ID[7:0]
0x000D 0x04 VENDOR_ID[15:8]
SPI_CFG 0x0010 0x01 Reserved (000000) VSPI[1:0]
OM1 0x0012 0x81 DF Res (00) IDLE[1:0] SYS_EN Res(01)
OM2 0x0013 0x40 Reserved (010) CLKDIV Res (0) Res (0) Res (0)
IMB_ADJ_A 0x0014 0x00 Res (0) AMPADJ_A[2:0] PHADJ_A[3:0]
IMB_ADJ_B 0x0015 0x00 Res (0) AMPADJ_B[2:0] PHADJ_B[3:0]
Address 0x0016-0x0018 Reserved
CDLY_CTRL 0x0019 0x00 Reserved (000) CDLY_EN CRS_DLY[3:0]
Address 0x001A-0x003A Reserved
OVR_HOLD 0x003B 0x00 Reserved (000000) OVR_HOLD[1:0]
OVR_TH 0x003C 0x00 OVR_TH[7:0]
DC_MODE 0x003D 0x00 Reserved (00000) DC_TC DC_EN
Address 0x003E-0x0046 Reserved
SER_CFG 0x0047 0x00 Res(0) VOD[2:0] Res (0) DEM[2:0]
Address 0x0048-0x005F Reserved
JESD_CTRL1 0x0060 0x7D SCR _EN K_M1[4:0] L_M1 JESD _EN
JESD_CTRL2 0x0061 0x00 Reserved (0000) JESD_TEST_MODE[3:0]
JESD_RSTEP 0x0062 0x01 JESD_RSTEP[7:0]
0x0063 0x00 JESD_RSTEP[15:8]
Address 0x0064-0x006B Reserved
JESD_STATUS 0x006C N/A Res (0) LINK SYNC REALIGN ALIGN PLL _LOCK CAL _DONE CLK _RDY
Address 0x006D-0x006F Reserved
DATA_CTRL 0x0070 0x22 Reserved (00100) TEST_DATA Res (1) Res (0)
Address 0x0071- Reserved

8.5.1 Register Descriptions

Table 7. CONFIG_A

CONFIG_A Address: 0x0000 Default: 0x3C
Bit Bit Name Read or Write Def Description
[7] SR Read or write 0 Setting this soft reset bit causes all registers to be reset to their default state. This bit is self-clearing.
[6] Reserved Read or write 0 Reserved and must be written with 0.
[5] ASCEND Read or write 1 Order of address change during streaming reads or writes.
0 : Address is decremented during streaming reads or writes.
1 : Address is incremented during streaming reads or writes (default).
[4] Reserved Read 1 Reserved and must be written with 1.
[3:0] PAL[3:0] Read or write 1100 Palindrome bits are bit 3 = bit 4, bit 2 = bit 5, bit 1 = bit 6, and bit 0 = bit 7.

Table 8. DEVICE CONFIG

DEVICE CONFIG Address: 0x0002 Default: 0x00
Bit Bit Name Read or Write Def Description
[7:2] Reserved Read or write 000000 Reserved and must be written with 000000.
[1:0] PD_MODE [1:0] Read or write 00 Power-down mode
00 : Normal operation (default)
01 : Reserved
10 : Sleep operation (faster resume)
11 : Power-down (slower resume)

Table 9. CHIP_TYPE

CHIP_TYPE Address: 0x0003 Default: 0x03
Bit Bit Name Read or Write Def Description
[7:4] Reserved Read or write 0000 Reserved and must be written with 0000.
[3:0] CHIP_TYPE[3:0] Read 0011 Chip type that always returns 0x3, indicating that the part is a high-speed ADC

Table 10. CHIP_ID

CHIP_ID Addresses: [0x0005, 0x0004] Default: [0x00, 0x02]
Bit Bit Name Read or Write Def Description
0x0004[7:0] CHIP_ID[7:0] Read 0x02 Chip ID least significant word
0x0005[7:0] CHIP_ID[15:8] Read 0x00 Chip ID most significant word

Table 11. CHIP_VERSION

CHIP_VERSION Address: 0x0006 Default: 0x01
Bit Bit Name Read or Write Def Description
[7:0] CHIP_VERSION[7:0] Read 0x01 Chip version

Table 12. VENDOR_ID

VENDOR_ID Addresses: [0x000D, 0x000C] Default: [0x04, 0x51]
Bit Bit Name Read or Write Def Description
0x000C[7:0] VENDOR_ID[7:0] Read 0x51 Vendor ID. Texas Instruments vendor ID is 0x0451.
0x000D[7:0] VENDOR_ID[15:8] Read 0x04

Table 13. SPI_CFG

SPI_CFG Address: 0x0010 Default: 0x01
Bit Bit Name Read or Write Def Description
[7:2] Reserved Read or write 000000 Reserved and must be written with 000000.
[1:0] VSPI Read or write 01 SPI logic level controls the SDO output logic level.
00 : 1.2 V
01 : 3 V (default)
10 : 2.5 V
11 : 1.8 V
This register must be configured (written) before making a read command with a SPI that is not a 3-V logic level. The SPI inputs (SDI, SCLK, and CSb) are compatible with logic levels ranging from 1.2 to 3 V.

Table 14. OM1 (Operational Mode 1)

OM1 (Operational Mode 1) Address: 0x0012 Default: 0x81
Bit Bit Name Read or Write Def Description
[7] DF Read or write 1 Output data format
0 : Offset binary
1 : Signed 2s complement (default)
[6:5] Reserved Read or write 00 Reserved and must be written with 00.
[4:3] IDLE[1:0] Read or write 00 SYSREF idle state offset configuration.
00 : No offset applied (default)
01 : SYSREF idles low (de-asserted) with –400-mV offset
10 : SYSREF idles high (asserted) with +400-mV offset
11 : Reserved
[2] SYS_EN Read or write 0 SYSREF detection gate enable
0 : SYSREF gate is disabled; (input is ignored, default)
1 : SYSREF gate is enabled
[1:0] Reserved[1:0] Read or write 01 Reserved. Must be written with 01.

Table 15. OM2 (Operational Mode 2)

OM2 (Operational Mode 2) Address: 0x0013 Default: 0x40
Bit Bit Name Read or Write Def Description
[7:5] Reserved Read or write 010 Reserved and must be written with 100.
[4:3] CLKDIV[1:0] Read or write 00 Clock divider ratio. Sets the value of the clock divide factor, CLKDIV
00 : Divide by 1, CLKDIV = 1 (default)
01 : Divide by 2, CLKDIV = 2
10 : Divide by 4, CLKDIV = 4
11 : Divide by 8, CLKDIV = 8
[2:0] Reserved Read or write 000 Reserved. Must be written with 000.

Table 16. IMB_ADJ_A (Imbalance Adjust, Channel A)

IMB_ADJ_A (Imbalance Adjust, Channel A) Address: 0x0014 Default: 0x00
Bit Bit Name Read or Write Def Description
[7] Reserved Read or write 0 Reserved. Must be written with 0.
[6:4] AMPADJ_A[2:0] Read or write 000 Analog input amplitude imbalance correction for channel A
7 = +30 Ω VIN+, –30 Ω VIN–
6 = +20 Ω VIN+, –20 Ω VIN–
5 = +10 Ω VIN+, –10 Ω VIN–
4 = Reserved
3 = –30 Ω VIN+, +30 Ω VIN–
2 = –20 Ω VIN+, +20 Ω VIN–
1 = –10 Ω VIN+, +10 Ω VIN–
0 = +0 Ω VIN+, –0 Ω VIN– (default)
Resistance changes indicate variation of the internal single-ended termination.
[3:0] PHADJ_A[3:0] Read or write 0000 Analog input phase imbalance correction for channel B
15 = +1.68 pF VIN–
...
9 = +0.48 pF VIN–
8 = +0.24 pF VIN–
7 = +1.68 pF VIN+
...
2 = +0.48 pF VIN+
1 = +0.24 pF VIN+
0 = +0 pF VIN+, +0 pF VIN– (default)
Capacitance changes indicate the addition of internal capacitive load on the given pin.

Table 17. IMB_ADJ_B (Imbalance Adjust, Channel B)

IMB_ADJ_B (Imbalance Adjust, Channel B) Address: 0x0015 Default: 0x00
Bit Bit Name Read or Write Def Description
[7] Reserved Read or write 0 Reserved and must be written with 0.
[6:4] AMPADJ_B[2:0] Read or write 000 Analog input amplitude imbalance correction for channel B. See description for IMB_ADJ_A.
[3:0] PHADJ_B[3:0] Read or write 0000 Analog input phase imbalance correction for channel B. See description for IMB_ADJ_A.

Table 18. CDLY_CTRL (Coarse Delay Control)

CDLY_CTRL (Coarse Delay Control) Address: 0x0019 Default: 0x00
Bit Bit Name Read or Write Def Description
[7:5] Reserved Read or write 000 Reserved and must be written as 000.
[4] CDLY_EN Read or write 0 Coarse sampling clock phase delay enable
0 : Coarse clock delay disabled (default)
1 : Coarse clock delay enabled
Coarse delay is not supported when the divide ratio is set to 1 (CLKDIV = 00).
[3:0] CRS_DLY[3:0] Read or write 0000 Coarse sampling clock phase delay adjust. Adjusts the ADC clock delay in coarse increments. The step size is one-half of the CLKIN input period.
Coarse Clock Delay (in units of CLKIN periods)
CRS_DLY CLKDIV = 11 (divide by 8) CLKDIV = 10 (divide by 4) CLKDIV = 01 (divide by 2) CLKDIV = 00 (divide by 1)
0000 (default) 1 1 1 Reserved. Coarse delay disabled for CLKDIV = 00 (divide by 1)
0001 1.5 1.5 1.5
0010 2 2 0
0011 2.5 2.5 0.5
0100 3 3 Reserved
0101 3.5 3.5
0110 4 0
0111 4.5 0.5
1000 5 Reserved
1001 5.5
1010 6
1011 6.5
1100 7
1101 7.5
1110 0
1111 0.5

Note:

  • When the setting is 0000 (default), the delay is 1 device clock, not 0.
  • Do not change the coarse delay when the ADC calibration is running.
  • The coarse delay adjustment is common to both channel A and B.
  • Increasing the coarse clock delay increases the delay between the input clock and the sampling instant but decreases the latency between the sampling instant and the transmitted data.

Table 19. OVR_HOLD (Over-Range Hold)

OVR_HOLD (Over-Range Hold) Address: 0x003B Default: 0x00
Bit Bit Name Read or Write Def Description
[7:2] Reserved Read or write 000000 Reserved and must be written as 000000.
[1:0] OVR_HOLD[1:0] Read or Write 00 Over-range hold function. In the event of an input signal larger than the full-scale range, an over-range event occurs and the over-range indicators are asserted. OVR_HOLD determines the amount of time the over-range indicators remain asserted after the input signal has reduced below full-scale.
00 : OVR indicator extended by +0 clock cycles (default)
01 : OVR indicator extended by +3 clock cycles
10 : OVR indicator extended by +7 clock cycles
11 : OVR indicator extended by +15 clock cycles
Note:
  • The unit of clock cycles corresponds to the period of the internal sampling clock.
  • The over-range indicators also experience a latency from when the over-range signal is sampled to when the indicator is asserted or de-asserted.

Table 20. OVR_TH (Over-Range Threshold)

OVR_TH (Over-Range Threshold) Address: 0x003C Default: 0x00
Bit Bit Name Read or Write Def Description
[7:0] OVR_TH[7:0] Read or write 00000000 Over-range threshold. This field is an unsigned value from 0 to 255. OVR_TH sets the over-range detection thresholds for the ADC. If the 16-bit signed data exceeds the thresholds, then the over-range bit is set. The 16-bit thresholds are ± OVR_TH × 128 codes from the low and high full-scale codes (32767 and –32768 in signed 2s complement). If OVR_TH is 0, then the default threshold is used (full scale).
OVR_TH 16-bit Threshold Threshold Relative to Peak Full Scale [dB]
2 Complement Offset Binary
255 (0xFF) ±32640 65408 / 128 –0.03
254 (0xFE) ±32512 65280 / 256 –0.07
...
128 (0x80) ±16384 49152 / 16,384 –6.02
...
2 (0x02) ±256 33024 / 32512 –42.14
1 (0x01) ±128 32896 / 32640 –48.16
0 (0x00) (default) +32767 / –32768 65535 / 0 –0.0

Table 21. DC_MODE (DC Offset Correction Mode)

DC_MODE (DC Offset Correction Mode) Address: 0x003D Default: 0x00
Bit Bit Name Read or Write Def Description
[7:3] Reserved Read or write 000000 Reserved and must be written as 00000.
[2:1] TC_DC Read or write 00 DC offset filter time constant.
The time constant determines the filter bandwidth of the DC high-pass filter.
TC_DC Time Constant
(FS = 370 MSPS)
3-dB Bandwidth
(FS = 370 MSPS)
3-dB Bandwidth (Normalized)
00 11 µs 14 kHz 37e–6 × Fs
01 89 µs 1.8 kHz 4.9e–6 × Fs
10 708 µs 224 Hz 605e–9 × Fs
11 5.7 ms 28 Hz 76e–9 × Fs
[0] DC_EN Read or Write 0 DC offset correction enable
0 : Disable DC offset correction
1 : Enable DC offset correction

Table 22. SER_CFG (Serial Lane Transmitter Configuration)

SER_CFG (Serial Lane Transmitter Configuration) Address: 0x0047 Default: 0x00
Bit Bit Name Read or Write Def Description
[7] Reserved Read or write 0 Reserved. Must be written as 0.
[6:4] VOD[2:0] Read or write 000 Serial-lane transmitter driver output differential peak-to-peak voltage amplitude.
000 : 0.580 V (default)
001 : 0.680 V
010 : 0.760 V
011 : 0.860 V
100 : 0.960 V
101 : 1.060 V
110 : 1.140 V
111 : 1.240 V
Reported voltage values are nominal values at low-lane rates with de-emphasis disabled
[3] Reserved Read or write 0 Reserved and must be written as 0.
[2:0] DEM[2:0] Read or write 000 Serial lane transmitted de-emphasis.
DEM De-emphasis [dB]
000 0
001 –0.4
010 –1.2
011 –2.1
100 –2.8
101 –3.8
110 –4.8
111 –6.8

Table 23. JESD_CTRL1 (JESD Configuration Control 1)

JESD_CTRL1 (JESD Configuration Control 1) Address: 0x0060 Default: 0x7D
Note: Before altering any parameters in this register, one must set JESD_EN = 0. Changing parameters while JESD_EN = 1 is not supported.
Bit Bit Name Read or Write Def Description
[7] SCR_EN Read or write 0 Scrambler enable.
0 : Disabled (default)
1 : Enabled
Note:
  • JESD_EN must be set to 0 before altering this field.
[6:2] K_M1[4:0] Read or write 11111 Number of frames per multi-frame, K – 1.
The binary values of K_M1 represent the value (K – 1)
00000 : Reserved
00001 : Reserved

00111 : Reserved
01000 : K = 9

11111 : K = 32 (default)
Note:
  • In single-lane mode, K must be in the range 9 to 32. Values outside this range are either reserved or may produce unexpected results.
  • In dual-lane mode, K must be in the range 17 to 32. Values outside this range are either reserved or may produce unexpected results.
  • JESD_EN must be set to 0 before altering this field.
[1] L_M1 Read or write 0 Number of serial lanes used per channel, L –1.
The binary value of L_M1 represents the value (L – 1).
0 : Single-lane mode (L = 1) (default)
1 : Dual-lane mode (L = 2)
Note:
  • If dual-lane mode is selected (L_M1 = 1) then K_M1 must be updated accordingly.
  • JESD_EN must be set to 0 before altering this field.
[0] JESD_EN Read or write 1 JESD204B link enable.
When enabled, the JESD204B link synchronizes and transfers data normally. When the link is disabled, the serial transmitters output a repeating, alternating 01010101 stream.
0 : Disabled
1 : Enabled (default)

Table 24. JESD_CTRL2 (JESD Configuration Control 2)

JESD_CTRL2 (JESD Configuration Control 2) Address: 0x0061 Default: 0x00
Note: Before altering any parameters in this register, one must set JESD_EN = 0. Changing parameters while JESD_EN = 1 is not supported.
Bit Bit Name Read or Write Def Description
[7:4] Reserved Read or write 0000 Reserved. Must be written as 0000.
[3:0] JESD_TEST_MODES[3:0] Read or write 0000 JESD204B test modes.
0000 : Test mode disabled. Normal operation (default)
0001 : PRBS7 test mode
0010 : PRBS15 test mode
0011 : PRBS23 test mode
0100 : RESERVED
0101 : ILA test mode
0110 : Ramp test mode
0111 : K28.5 test mode
1000 : D21.5 test mode
1001: Logic low test mode (serial outputs held low)
1010: Logic high test mode (serial outputs held high)
1011 – 1111 : Reserved
Note:
  • JESD_EN must be set to 0 before altering this field.

Table 25. JESD_RSTEP (JESD Ramp Pattern Step)

JESD_RSTEP (JESD Ramp Pattern Step) Addresses: [0x0063, 0x0062] Default: [0x00, 0x01]
Bit Bit Name Read or Write Def Description
0x0062[7:0] JESD_RSTEP[7:0] Read or write 0x01 JESD204B ramp test mode step
0x0063[7:0] JESD_RSTEP[15:8] Read or write 0x00 The binary value JESD_RSTEP[15:0] corresponds to the step of the ramp mode step. A value of 0x0000 is not allowed.
Note:
  • JESD_EN must be set to 0 before altering this field.

Table 26. JESD_STATUS (JESD Link Status)

JESD_STATUS (JESD Link Status) Address: 0x006C Default: N/A
Bit Bit Name Read or Write Def Description
[7] Reserved Read N/A Reserved.
[6] LINK Read N/A JESD204B link status
This bit is set when synchronization is finished, transmission of the ILA sequence is complete, and valid data is being transmitted.
0 : Link not established
1 : Link established and valid data transmitted
[5] SYNC Read N/A JESD204B link synchronization request status
This bit is cleared when a synchronization request is received at the SYNCb input.
0 : Synchronization request received at the SYNCb input and synchronization is in progress
1 : Synchronization not requested
Note:
  • SYNCb must be asserted for at least four local frame clocks before synchronization is initiated. The SYNC status bit reports the status of synchronization, but does not necessarily report the current status of the signal at the SYNCb input.
[4] REALIGN Read or write N/A SYSREF re-alignment status
This bit is set when a SYSREF event causes a shift in the phase of the internal frame or LMFC clocks.
Note:
  • Write a 1 to REALIGN to clear the bit field to a 0 state.
  • SYSREF events that do not cause a frame or LMFC clock phase adjustment do not set this register bit.
  • If CLK_RDY becomes low, this bit is cleared.
[3] ALIGN Read or write N/A SYSREF alignment status
This bit is set when the ADC has processed a SYSREF event and indicates that the local frame and multi-frame clocks are now based on a SYSREF event.
Note:
  • Write a 1 to ALIGN to clear the bit field to a 0 state.
  • Rising-edge SYSREF event sets ALIGN bit.
  • If CLK_RDY becomes low, this bit is cleared.
[2] PLL_LOCK Read N/A PLL lock status. This bit is set when the PLL has achieved lock.
0 : PLL unlocked
1 : PLL locked
[1] CAL_DONE Read N/A ADC calibration status
This bit is set when the ADC calibration is complete.
0 : Calibration currently in progress or not yet completed
1 : Calibration complete
Note:
  • Calibration must complete before SYSREF detection (SYS_EN) can be enabled.
  • Calibration must complete before the any clock phase delay adjustments are made.
[0] CLK_RDY Read N/A Input clock status
This bit is set when the ADC is powered-up and detects an active clock signal at the CLKIN input.
0 : CLKIN not detected
1 : CLKIN detected

Table 27. DATA_CTRL (Output Data Source Control)

DATA_CTRL (Output Data Source Control) Address: 0x0070 Default: 0x22
Bit Bit Name Read or Write Def Description
[7:3] Reserved Read or write 00100 Reserved and must be written as 00100
[2] TEST_DATA Read or write 0 ADC test pattern enable
When enabled, data from the ADC core is replaced by test pattern data. The pattern is a 16-bit repeating [0, 26280, 0, –26328] sequence (signed 16-bit number) that appears in the FFT spectrum as a tone, centered at FS / 4, and just below the clipping level.
0 : Disabled ADC test pattern (default)
1 : Enable ADC test pattern
Note:
  • The ADC test pattern function is independent from the test patterns outlined in the JESD_CTRL2 register. The TEST_DATA bit enables a test pattern at the ADC core output, prior to entering the JESD204B core. The JESD_TEST_MODES field enables test patterns within the transport and link layers of the JESD204B core.
[1] Reserved Read or write 1 Reserved and must be written as 1
[0] Reserved Read or write 0 Reserved and must be written as 0