ZHCSI83C may 2018 – may 2023 ADC12DL3200
PRODUCTION DATA
The ADC12DL3200 is able to achieve multi-device synchronization through deterministic latency across the LVDS interface. First, SYSREF is issued to all devices as a known timing reference for synchronization. SYSREF resets internal clock dividers and the strobe generation block within the ADC12DL3200. The ADC12DL3200 issues strobe signals across each bus of the interface to provide timing information to the receiver. The receiver uses this timing information to achieve fixed latency and for alignment among multiple ADC12DL3200 devices. The strobe generator block provides internal generation of a repeating strobe signal to reflect the end of a data frame. The generated strobe can be sent across the interface using a dedicated LVDS pair (DxSTR±) or as a replacement of the sample LSB with the strobe. Strobe generation can be controlled by the SYNC signal through the SPI or by using the SYNCSE or TMSTP± inputs (see SYNC_SEL in the LCTRL register). In all modes, the strobe output can be treated as a data pair with the same timing as the data outputs (Dx[11:0]±) that is source-synchronous with the associated data clock (DxCLK±).
The strobe generator sets the last unit interval (UI) of a frame high to signal the end of a frame. Frame length is programmable through the LFRAME register. The SYSREF input marks the start of a frame and, if run periodically, then the SYSREF period must be an integer number of frames long.