ZHCSGK9A April 2017 – July 2017 TPS22971

PRODUCTION DATA.

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

It is recommended to limit the junction temperature (T_{J}) to below 125°C. To calculate the maximum allowable dissipation, P_{D(max)} for a given output current and ambient temperature, use Equation 6 as a guideline:

Equation 6.

where

- P
_{D(max)}is maximum allowable power dissipation - T
_{J(max)}is maximum allowable junction temperature - T
_{A}is ambient temperature of the device - Θ
_{JA}is junction to air thermal impedance. See the*Thermal Information*section. This parameter is highly dependent upon board layout

The PG output is an open drain signal which connects to a voltage source through a pull up resistor R_{PU}. The PG signal can be used to drive the enable pins of downstream devices, EN. PG is active high, and its voltage is given by Equation 7.

Equation 7.

where

- V
_{OUT}is the voltage where PG is tied to - I
_{PG,LK}is the leakage current into PG pin - I
_{EN,LK}is the leakage current into the EN pin driven by PG - R
_{PU}is the pull up resistance

V_{PG} needs to be higher than V_{IH,MIN} of the EN pin to be treated as logic high. The maximum R_{PU} is determined by Equation 8.

Equation 8.

When PG is disabled, with 1 mA current into PG pin (IPG = 1 mA), V_{PG.OL} is less than 0.2 V and treated as logic low as long as V_{IL,MAX} of the EN pin is greater than 0.2 V. The minimum R_{PU} is determined by Equation 9.

Equation 9.

R_{PU} can be chosen within the range defined by R_{PU,MIN} and R_{PU,MAX}. R_{PU} = 10 kΩ is used for characterization.

The TPS22971 has an integrated power good indicator which can be used for power sequencing. As shown in Figure 26, the switch to the second load is controlled by the PG signal from the first switch. This ensures that the power to load 2 is only enabled after the same power to load 1 is enabled after the first switch has turned on.

For this design example, below, use the input parameters shown in Table 2.

DESIGN PARAMETER | EXAMPLE VALUE |
---|---|

V_{IN} | 3.6 V |

I_{LOAD} | 10 mA |

Load Capacitance (C_{L}) | 33 μF |

Maximum Voltage Drop | 1% |

Maximum Inrush Current | 630 mA |

At 3.6-V input voltage, with a maximum voltage drop tolerance of 1%, the TPS22971 has a typical R_{ON} of 6.7 mΩ. The rail is supplying 10 mA of current; the voltage drop for a rail is calculated based on Equation 10.

Equation 10.

Equation 11.

The maximum voltage drop is 1% which is 36 mV. The voltage drop caused by the load current across the on resistance is 0.067 mV.

When the switch is enabled, the output capacitors must be charged up from 0 V to V_{IN}. This charge arrives in the form of inrush current. Given a load capacitance (C_{L}) of 33 μF, an input voltage (V_{IN}) of 3.6V and a maximum inrush (I_{INRUSH}) of 630 mA, use Equation 12 and Equation 13 to solve for Slew Rate (SR).

Equation 12.

Equation 13.

Now that the desired slew rate has been calculated, use SR and V_{IN} in in Equation 14 to calculate a CT capacitance value.

Equation 14.

A capacitance value of 1007pF is a non-standard value therefore a 1000 pF CT capacitance is used moving forward.

The calculated CT value can be used with Equation 2 and Equation 4 to determine t_{ON} and t_{PG,ON}, respectively as shown in Equation 15 and Equation 16.

Equation 15.

Equation 16.

V_{IN} = 3.6 V | V_{ON} = 3.6 V | C_{IN} = 1 µF |

R_{L} = OPEN | T_{A} = 25°C | C_{L} = 33 µF |

V_{IN} = 3.6 V | V_{ON} = 3.6 V | C_{IN} = 1 µF |

R_{L} = OPEN | T_{A} = 25°C | C_{L} = 33 µF |