ZHCSFY2A August 2015  – November 2016 TAS2555

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 SPI Timing Requirements
    8. 7.8 I2S/LJF/RJF Timing in Master Mode
    9. 7.9 I2S/LJF/RJF Timing in Slave Mode
    10. 7.10DSP Timing in Master Mode
    11. 7.11DSP Timing in Slave Mode
    12. 7.12Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 General I2C Operation
      2. 9.3.2 Single-Byte and Multiple-Byte Transfers
      3. 9.3.3 Single-Byte Write
      4. 9.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.3.5 Single-Byte Read
      6. 9.3.6 Multiple-Byte Read
      7. 9.3.7 General SPI Operation
      8. 9.3.8 Class-D Edge Rate Control
      9. 9.3.9 Battery Tracking AGC
      10. 9.3.10Configurable Boost Current Limit (ILIM)
        1. 9.3.10.1Fault Protection
          1. 9.3.10.1.1OverCurrent
          2. 9.3.10.1.2Analog Undervoltage
          3. 9.3.10.1.3Overtemperature
          4. 9.3.10.1.4Clocking Faults
        2. 9.3.10.2Brownout
        3. 9.3.10.3Spread Spectrum vs Synchronized
        4. 9.3.10.4IRQs and Flags
        5. 9.3.10.5Software Reset
        6. 9.3.10.6PurePath Console 3 Software TAS2555 Application
    4. 9.4Device Functional Modes
      1. 9.4.1Audio Digital I/O Interface
        1. 9.4.1.1Right-Justified Mode (RJF)
        2. 9.4.1.2Left-Justified Mode (LJF)
        3. 9.4.1.3I2S Mode
        4. 9.4.1.4DSP Mode
      2. 9.4.2TDM Mode
      3. 9.4.3Device Digital Processing Modes
        1. 9.4.3.1ROM Mode 1
        2. 9.4.3.2ROM Mode 2
        3. 9.4.3.3SmartAmp Mode
      4. 9.4.4Low Power Sleep Mode
    5. 9.5Programming
      1. 9.5.1Code Loading and CRC check
      2. 9.5.2Device Power Up, Power Down, Mute and Un-mute Sequence
  10. 10Applications and Implementation
    1. 10.1Application Information
    2. 10.2Typical Applications
      1. 10.2.1Design Requirements
        1. 10.2.1.1Detailed Design Procedure
          1. 10.2.1.1.1Mono/Stereo Configuration
          2. 10.2.1.1.2Boost Converter Passive Devices
          3. 10.2.1.1.3EMI Passive Devices
          4. 10.2.1.1.4Miscellaneous Passive Devices
      2. 10.2.2Application Performance Plots
    3. 10.3Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1Power Supplies
    2. 11.2Power Supply Sequencing
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Register Map
    1. 13.1Register Map Summary
    2. 13.2 Book 0 Page 0
      1. 13.2.1 Book 0 / Page 0 / Register 0: Page Select Register - 0x00 / 0x00 / 0x00 (B0_P0_R0)
      2. 13.2.2 Book 0 / Page 0 / Register 1: Software Reset Register - 0x00 / 0x00 / 0x01 (B0_P0_R1)
      3. 13.2.3 Book 0 / Page 0 / Register 2-3: Reserved Registers - 0x00 / 0x00 / 0x02-0x03 (B0_P0_R2-3)
      4. 13.2.4 Book 0 / Page 0 / Register 4: Power Control Register - 0x00 / 0x00 / 0x04 (B0_P0_R4)
      5. 13.2.5 Book 0 / Page 0 / Register 5: Power Control Register 2 - 0x00 / 0x00 / 0x05 (B0_P0_R5)
      6. 13.2.6 Book 0 / Page 0 / Register 6: Speaker Control Register - 0x00 / 0x00 / 0x06 (B0_P0_R6)
      7. 13.2.7 Book 0 / Page 0 / Register 7: Mute Register - 0x00 / 0x00 / 0x07 (B0_P0_R7)
      8. 13.2.8 Book 0 / Page 0 / Register 8: Channel Control Register - 0x00 / 0x00 / 0x08 (B0_P0_R8)
      9. 13.2.9 Book 0 / Page 0 / Register 9-31: Reserved Registers - 0x00 / 0x00 / 0x09-0x1F (B0_P0_R9-31)
      10. 13.2.10Book 0 / Page 0 / Register 32: CRC Checksum Register - 0x00 / 0x00 / 0x20 (B0_P0_R32)
      11. 13.2.11Book 0 / Page 0 / Register 33: Checksum Reset Register - 0x00 / 0x00 / 0x21 (B0_P0_R33)
      12. 13.2.12Book 0 / Page 0 / Register 34: Device DSP Mode Register - 0x00 / 0x00 / 0x22 (B0_P0_R34)
      13. 13.2.13Book 0 / Page 0 / Register 35-39: Reserved Registers - 0x00 / 0x00 / 0x23-0x27 (B0_P0_R35-R39)
      14. 13.2.14Book 0 / Page 0 / Register 40: Class-D SSM Mode Register - 0x00 / 0x00 / 0x28 (B0_P0_R40)
      15. 13.2.15Book 0 / Page 0 / Register 41: Reserved Registers - 0x00 / 0x00 / 0x29 (B0_P0_R41)
      16. 13.2.16Book 0 / Page 0 / Register 42: Digital Playback Control Register - 0x00 / 0x00 / 0x2A (B0_P0_R42)
      17. 13.2.17Book 0 / Page 0 / Register 43: Current Limit Register - 0x00 / 0x00 / 0x2B (B0_P0_R43)
      18. 13.2.18Book 0 / Page 0 / Register 44: Clock Error Control 1 Register - 0x00 / 0x00 / 0x2C (B0_P0_R44)
      19. 13.2.19Book 0 / Page 0 / Register 45: Clock Error Control 2 Register - 0x00 / 0x00 / 0x2D (B0_P0_R45)
      20. 13.2.20Book 0 / Page 0 / Register 46: Clock Error Control 3 Register - 0x00 / 0x00 / 0x2E (B0_P0_R46)
      21. 13.2.21Book 0 / Page 0 / Register 47-99: Reserved Registers - 0x00 / 0x00 / 0x2F-0x63 (B0_P0_R47-R99)
      22. 13.2.22Book 0 / Page 0 / Register 100: Power Up Flag Register - 0x00 / 0x00 / 0x64 (B0_P0_R100)
      23. 13.2.23Book 0 / Page 0 / Register 101-103: Reserved Registers - 0x00 / 0x00 / 0x65-0x67 (B0_P0_R101-R103)
      24. 13.2.24Book 0 / Page 0 / Register 104: Interrupt Flags DAC & OCP/OTP Sticky Register - 0x00 / 0x00 / 0x68 (B0_P0_R104)
      25. 13.2.25Book 0 / Page 0 / Register 105-107: Reserved Registers - 0x00 / 0x00 / 0x69-0x6B (B0_P0_R105-R107)
      26. 13.2.26Book 0 / Page 0 / Register 108: DSP Interrupt Output Sticky Register - 0x00 / 0x00 / 0x6C (B0_P0_R108)
      27. 13.2.27Book 0 / Page 0 / Register 109-120: Reserved Registers - 0x00 / 0x00 / 0x6D-0x78 (B0_P0_R109-R120)
      28. 13.2.28Book 0 / Page 0 / Register 121: Power Modes Register - 0x00 / 0x00 / 0x79 (B0_P0_R121)
      29. 13.2.29Book 0 / Page 0 / Register 122-126: Reserved Registers - 0x00 / 0x00 / 0x7A-0x7E (B0_P0_R122-R126)
      30. 13.2.30Book 0 / Page 0 / Register 127: Book Selection Register - 0x00 / 0x00 / 0x7F (B0_P0_R127)
    3. 13.3 Book 0 Page 1
      1. 13.3.1 Book 0 / Page 1 / Register 0: Page Select Register - 0x00 / 0x01 / 0x00 (B0_P1_R0)
      2. 13.3.2 Book 0 / Page 1 / Register 1: ASI1 DAC Format Register - 0x00 / 0x01 / 0x01 (B0_P1_R1)
      3. 13.3.3 Book 0 / Page 1 / Register 2: ASI1 ADC Format Register - 0x00 / 0x01 / 0x02 (B0_P1_R2)
      4. 13.3.4 Book 0 / Page 1 / Register 3: ASI1 Offset Register - 0x00 / 0x00 / 0x03 (B0_P1_R3)
      5. 13.3.5 Book 0 / Page 1 / Register 4-6: Reserved Registers - 0x00 / 0x01 / 0x04-0x06 (B0_P1_R4-6)
      6. 13.3.6 Book 0 / Page 1 / Register 7: ASI1 ADC Path Register - 0x00 / 0x01 / 0x07 (B0_P1_R7)
      7. 13.3.7 Book 0 / Page 1 / Register 8: ASI1 DAC BCLK Register - 0x00 / 0x01 / 0x08 (B0_P1_R8)
      8. 13.3.8 Book 0 / Page 1 / Register 9: ASI1 DAC WCLK Register - 0x00 / 0x01 / 0x09 (B0_P1_R9)
      9. 13.3.9 Book 0 / Page 1 / Register 10: ASI1 ADC BCLK Register - 0x00 / 0x01 / 0x0A (B0_P1_R10)
      10. 13.3.10Book 0 / Page 1 / Register 11: ASI1 ADC WCLK Register - 0x00 / 0x01 / 0x0B (B0_P1_R11)
      11. 13.3.11Book 0 / Page 1 / Register 12: ASI1 DIN/DOUT MUX Register - 0x00 / 0x01 / 0x0C (B0_P1_R12)
      12. 13.3.12Book 0 / Page 1 / Register 13: ASI1 BDIV Clock Select Register - 0x00 / 0x01 / 0x0D (B0_P1_R13)
      13. 13.3.13Book 0 / Page 1 / Register 14: ASI1 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x0E (B0_P1_R14)
      14. 13.3.14Book 0 / Page 1 / Register 15: ASI1 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x0F (B0_P1_R15)
      15. 13.3.15Book 0 / Page 1 / Register 16: ASI1 DAC Clock Output Register - 0x00 / 0x01 / 0x10 (B0_P1_R16)
      16. 13.3.16Book 0 / Page 1 / Register 17: ASI1 ADC Clock Output Register - 0x00 / 0x01 / 0x11 (B0_P1_R17)
      17. 13.3.17Book 0 / Page 1 / Register 18-20: Reserved Registers - 0x00 / 0x01 / 0x12-0x14 (B0_P1_R18-20)
      18. 13.3.18Book 0 / Page 1 / Register 21: ASI2 DAC Format Register - 0x00 / 0x01 / 0x15 (B0_P1_R21)
      19. 13.3.19Book 0 / Page 1 / Register 22: ASI2 ADC Format Register - 0x00 / 0x01 / 0x16 (B0_P1_R22)
      20. 13.3.20Book 0 / Page 1 / Register 23: ASI2 Offset Register - 0x00 / 0x01 / 0x17 (B0_P1_R23)
      21. 13.3.21Book 0 / Page 1 / Register 24-26: Reserved Registers - 0x00 / 0x01 / 0x18-0x1A (B0_P1_R24-26)
      22. 13.3.22Book 0 / Page 1 / Register 27: ASI2 ADC Path Register - 0x00 / 0x01 / 0x1B (B0_P1_R27)
      23. 13.3.23Book 0 / Page 1 / Register 28: ASI2 DAC BCLK Register - 0x00 / 0x01 / 0x1C (B0_P1_R28)
      24. 13.3.24Book 0 / Page 1 / Register 29: ASI2 DAC WCLK Register - 0x00 / 0x01 / 0x1D (B0_P1_R29)
      25. 13.3.25Book 0 / Page 1 / Register 30: ASI2 ADC BCLK Register - 0x00 / 0x01 / 0x1E (B0_P1_R30)
      26. 13.3.26Book 0 / Page 1 / Register 31: ASI2 ADC WCLK Register - 0x00 / 0x01 / 0x1F (B0_P1_R31)
      27. 13.3.27Book 0 / Page 1 / Register 32: ASI2 DIN/DOUT MUX - 0x00 / 0x01 / 0x20 (B0_P1_R32)
      28. 13.3.28Book 0 / Page 1 / Register 33: ASI2 BDIV Clock Select Register - 0x00 / 0x01 / 0x21 (B0_P1_R33)
      29. 13.3.29Book 0 / Page 1 / Register 34: ASI2 BDIV Clock Ratio Register - 0x00 / 0x01 / 0x22 (B0_P1_R34)
      30. 13.3.30Book 0 / Page 1 / Register 35: ASI2 WDIV Clock Ratio Register - 0x00 / 0x01 / 0x23 (B0_P1_R35)
      31. 13.3.31Book 0 / Page 1 / Register 36: ASI2 DAC Clock Output Register - 0x00 / 0x01 / 0x24 (B0_P1_R36)
      32. 13.3.32Book 0 / Page 1 / Register 37: ASI2 ADC Clock Output Register - 0x00 / 0x01 / 0x25 (B0_P1_R37)
      33. 13.3.33Book 0 / Page 1 / Register 38-60: Reserved Registers - 0x00 / 0x01 / 0x26-0x3C (B0_P1_R38-60)
      34. 13.3.34Book 0 / Page 1 / Register 61: BCLK1_GPIO1 Pin Register - 0x00 / 0x01 / 0x3D (B0_P1_R61)
      35. 13.3.35Book 0 / Page 1 / Register 62: WCLK1_GPIO2 Pin Register - 0x00 / 0x01 / 0x3E (B0_P1_R62)
      36. 13.3.36Book 0 / Page 1 / Register 63: DOUT1_GPIO3 Pin Register - 0x00 / 0x01 / 0x3F (B0_P1_R63)
      37. 13.3.37Book 0 / Page 1 / Register 64: IRQ_GPIO4 Pin Register - 0x00 / 0x01 / 0x40 (B0_P1_R64)
      38. 13.3.38Book 0 / Page 1 / Register 65: BCLK2_GPIO5 Pin Register - 0x00 / 0x01 / 0x41 (B0_P1_R65)
      39. 13.3.39Book 0 / Page 1 / Register 66: WCLK2_GPIO6 Pin Register - 0x00 / 0x01 / 0x42 (B0_P1_R66)
      40. 13.3.40Book 0 / Page 1 / Register 67: DOUT2_GPIO7 Pin Register - 0x00 / 0x01 / 0x43 (B0_P1_R67)
      41. 13.3.41Book 0 / Page 1 / Register 68: DIN2_GPIO8 Pin Register - 0x00 / 0x01 / 0x44 (B0_P1_R68)
      42. 13.3.42Book 0 / Page 1 / Register 69: ICC_GPIO9 Pin(ICC_CLK) Register - 0x00 / 0x01 / 0x45 (B0_P1_R69)
      43. 13.3.43Book 0 / Page 1 / Register 70: ICC_GPIO10 Pin Register - 0x00 / 0x01 / 0x46 (B0_P1_R70)
      44. 13.3.44Book 0 / Page 1 / Register 71-76: Reserved Registers - 0x00 / 0x01 / 0x47-0x4C (B0_P1_R71-76)
      45. 13.3.45Book 0 / Page 1 / Register 77: GPI Pins Register - 0x00 / 0x01 / 0x4D (B0_P1_R77)
      46. 13.3.46Book 0 / Page 1 / Register 78: Reserved Register - 0x00 / 0x01 / 0x4E (B0_P1_R78)
      47. 13.3.47Book 0 / Page 1 / Register 79: GPIO HIZ CTRL1 Register - 0x00 / 0x01 / 0x4F (B0_P1_R79)
      48. 13.3.48Book 0 / Page 1 / Register 80: GPIO HIZ CTRL2 Register - 0x00 / 0x01 / 0x50 (B0_P1_R80)
      49. 13.3.49Book 0 / Page 1 / Register 81: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x51 (B0_P1_R81)
      50. 13.3.50Book 0 / Page 1 / Register 82: GPIO HIZ CTRL4 Register - 0x00 / 0x01 / 0x52 (B0_P1_R82)
      51. 13.3.51Book 0 / Page 1 / Register 83: GPIO HIZ CTRL3 Register - 0x00 / 0x01 / 0x53 (B0_P1_R83)
      52. 13.3.52Book 0 / Page 1 / Register 84-86: Reserved Registers - 0x00 / 0x01 / 0x54-0x56 (B0_P1_R84-86)
      53. 13.3.53Book 0 / Page 1 / Register 87: GPIO Pin 1 Register - 0x00 / 0x01 / 0x57 (B0_P1_R87)
      54. 13.3.54Book 0 / Page 1 / Register 88: GPIO Pin 2 Register - 0x00 / 0x01 / 0x58 (B0_P1_R88)
      55. 13.3.55Book 0 / Page 1 / Register 89: GPIO Pin 3 Register - 0x00 / 0x01 / 0x59 (B0_P1_R89)
      56. 13.3.56Book 0 / Page 1 / Register 90-107: Reserved Registers - 0x00 / 0x01 / 0x5A-0x6B (B0_P1_R84-86)
      57. 13.3.57Book 0 / Page 1 / Register 108: Interrupt Control 1 Register - 0x00 / 0x01 / 0x6C (B0_P1_R108)
      58. 13.3.58Book 0 / Page 1 / Register 109: Interrupt Control 2 Register - 0x00 / 0x01 / 0x6D (B0_P1_R109)
      59. 13.3.59Book 0 / Page 1 / Register 110: Interrupt Control 3 Register - 0x00 / 0x01 / 0x6E (B0_P1_R110)
      60. 13.3.60Book 0 / Page 1 / Register 111: Interrupt Control 4 Register - 0x00 / 0x01 / 0x6F (B0_P1_R111)
      61. 13.3.61Book 0 / Page 1 / Register 112: Interrupt Control 5 Register - 0x00 / 0x01 / 0x70 (B0_P1_R112)
      62. 13.3.62Book 0 / Page 1 / Register 113: Interrupt Control 6 Register - 0x00 / 0x01 / 0x71 (B0_P1_R113)
      63. 13.3.63Book 0 / Page 1 / Register 114-127: Reserved Register - 0x00 / 0x01 / 0x72-0x7F (B0_P1_R127)
    4. 13.4 Book 0 Page 2
      1. 13.4.1Book 0 / Page 2 / Register 0: Page Select Register - 0x00 / 0x02 / 0x00 (B0_P0_R0)
      2. 13.4.2Book 0 / Page 2 / Register 1-5: Reserved Register - 0x00 / 0x02 / 0x01-0x05 (B0_P1_R1-5)
      3. 13.4.3Book 0 / Page 2 / Register 6: Ramp Generator Frequency Register - 0x00 / 0x02 / 0x06 (B0_P2_R6)
      4. 13.4.4Book 0 / Page 2 / Register 7-23: Reserved Register - 0x00 / 0x02 / 0x07-0x17 (B0_P1_R7-23)
      5. 13.4.5Book 0 / Page 2 / Register 24: Inrush Optimization 1 Register - 0x00 / 0x02 / 0x18 (B0_P2_R24)
      6. 13.4.6Book 0 / Page 2 / Register 25: Inrush Optimization 2 Register - 0x00 / 0x02 / 0x19 (B0_P2_R25)
      7. 13.4.7Book 0 / Page 2 / Register 26: Inrush Optimization 3 Register - 0x00 / 0x02 / 0x1A (B0_P2_R25)
      8. 13.4.8Book 0 / Page 2 / Register 27: Inrush Optimization 4 Register - 0x00 / 0x02 / 0x1B (B0_P2_R25)
      9. 13.4.9Book 0 / Page 2 / Register 28-127: Reserved Register - 0x00 / 0x02 / 0x1C-0x7F (B0_P1_R28-127)
    5. 13.5 Book 100 Page 0
      1. 13.5.1 Book 100 / Page 0 / Register 0: Page Select Register - 0x64 / 0x00 / 0x00 (B100_P0_R0)
      2. 13.5.2 Book 100 / Page 0 / Register 1: DAC Interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      3. 13.5.3 Book 100 / Page 0 / Register 2: ADC interpolation Register - 0x64 / 0x00 / 0x01 (B100_P0_R1)
      4. 13.5.4 Book 100 / Page 0 / Register 3-6: Reserved Register - 0x64 / 0x00 / 0x03-0x06 (B100_P0_R3-6)
      5. 13.5.5 Book 100 / Page 0 / Register 7: DSP Mute Register - 0x64 / 0x00 / 0x07 (B100_P0_R7)
      6. 13.5.6 Book 100 / Page 0 / Register 8-15: Reserved Register - 0x64 / 0x00 / 0x08-0x0F (B100_P0_R8-15)
      7. 13.5.7 Book 100 / Page 0 / Register 16: Interrupt 1 DSP Register - 0x64 / 0x00 / 0x10 (B100_P0_R16)
      8. 13.5.8 Book 100 / Page 0/ Register 17: Interrupt 2 DSP Register - 0x64 / 0x00 / 0x11 (B100_P0_R17)
      9. 13.5.9 Book 100 / Page 0 / Register 18: Condition 1 DSP Register - 0x64 / 0x00 / 0x12 (B100_P0_R18)
      10. 13.5.10Book 100/ Page 0 / Register 19: Condition 2 DSP Register - 0x64 / 0x00 / 0x13 (B100_P0_R19)
      11. 13.5.11Book 100 / Page 0 / Register 20: ISR and COND Control Register - 0x64 / 0x00 / 0x14 (B100_P0_R20)
      12. 13.5.12Book 100 / Page 0/ Register 21: DSP Control Register - 0x64 / 0x00 / 0x15 (B100_P0_R21)
      13. 13.5.13Book 100 / Page 0 / Register 22-26: Reserved Register - 0x64 / 0x00 / 0x16-0x1A (B100_P0_R22-26)
      14. 13.5.14Book 100 / Page 0 / Register 27:PLL CLKIN Divider Register - 0x64 / 0x00 / 0x1B (B100_P0_R27)
      15. 13.5.15Book 100 / Page 0 / Register 28:PLL J-VAL Divider Register - 0x64 / 0x00 / 0x1C (B100_P0_R28)
      16. 13.5.16Book 100 / Page 0 / Register 29:PLL D-VAL Divider 2 Register - 0x64 / 0x00 / 0x1D (B100_P0_R29)
      17. 13.5.17Book 100 / Page 0 / Register 30:PLL D-VAL Divider 1 Register - 0x64 / 0x00 / 0x1E (B100_P0_R30)
      18. 13.5.18Book 100 / Page 0 / Register 31:DSP Clock Register - 0x64 / 0x00 / 0x1F (B100_P0_R31)
      19. 13.5.19Book 100 / Page 0 / Register 32: N-VAL Divider Register - 0x64 / 0x00 / 0x20 (B100_P0_R32)
      20. 13.5.20Book 100 / Page 0 / Register 33: MDAC-VAL Divider Register - 0x64 / 0x00 / 0x21 (B100_P0_R33)
      21. 13.5.21Book 100 / Page 0 / Register 34: MADC-VAL Divider Register - 0x64 / 0x00 / 0x22 (B100_P0_R34)
      22. 13.5.22Book 100 / Page 0 / Register 35-37: Reserved Register - 0x64 / 0x00 / 0x23-0x25 (B100_P0_R35-37)
      23. 13.5.23Book 100 / Page 0 / Register 38: Charge-pump Clock Register - 0x64 / 0x00 / 0x26 (B100_P0_R38)
      24. 13.5.24Book 100 / Page 0 / Register 39: Boost Clock Register - 0x64 / 0x00 / 0x27 (B100_P0_R39)
      25. 13.5.25Book 100 / Page 0 / Register 40: Ramp Clock 1 Register - 0x64 / 0x00 / 0x28 (B100_P0_R40)
      26. 13.5.26Book 100 / Page 0 / Register 41-42: Reserved Register - 0x64 / 0x00 / 0x29-0x2A (B100_P0_R41-42)
      27. 13.5.27Book 100 / Page 0 / Register 43: Ramp Clock 2 Register - 0x64 / 0x00 / 0x2B (B100_P0_R43)
      28. 13.5.28Book 100 / Page 0 / Register 44: Ramp Clock 3 Register - 0x64 / 0x00 / 0x2C (B100_P0_R44)
      29. 13.5.29Book 100 / Page 0/ Register 45-126: Reserved Register - 0x64 / 0x01 / 0x2D-0x7E (B100_P0_R45-126)
      30. 13.5.30Book 100 / Page 0 / Register 127: Book Selection Register - 0x64 / 0x00 / 0x7F (B100_P0_R127)
  14. 14器件和文档支持
    1. 14.1文档支持
    2. 14.2社区资源
    3. 14.3商标
    4. 14.4静电放电警告
    5. 14.5Glossary
  15. 15机械、封装和可订购信息
    1. 15.1封装尺寸

封装选项

机械数据 (封装 | 引脚)
  • YZ|42
订购信息

Detailed Description

Overview

The TAS2555 device is a state-of-the-art Class-D audio amplifier which is a full system on a Chip (SoC). The device features a ultra low-noise audio DAC and Class-D power amplifier which incorporates speaker voltage and current sensing feedback. An on-chip, low-latency DSP supports Texas Instruments SmartAmp speaker protection algorithms to maximizes loudness while maintaining safe speaker conditions. A smart integrated multi-level Class-H boost converter maximizes system efficiency at all times by tracking the required output voltage. The TAS2555 drives up to 3.8 W from a 4.2-V supply into an 8-Ω speaker with 1% THD, or up to up 5.7 W into a 4-Ω speaker with 1% THD.

The TAS2555 device, with final processed digital output, can also be used to increase loudness and clarity in both Noise Canceling / Echo Cancelling speaker phone applications as well as for music or other sound applications. The TAS2555 device supports analog inputs for applications such as FM chips with analog output only, but with reduction in performance and speaker protection. The TAS2555 device accepts input audio data rates from 8 kHz to 96 kHz using ROM modes to fully support both speaker-phone and music applications. When speaker protection system is running the maximum sampling rate is limited to 48 kHz.

The multi-level Class-H boost converter generates the Class-D amplifier supply rail. When the audio signal requires a output power below VBAT, the boost improves system efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When higher audio output power is required, the boost quickly activates and provides a much louder and much clearer signal than can be achieved in any standard amplifier speaker system design approach. A boost inductor of 1uH can be used with a slight increase in boost ripple.

On-chip brown out detection system shutdown down audio at the user configurable threshold to avoid undesired system reset. In addition, an AGC can be selected to minimize clipping events when a lower power supply voltage is provided to the Class-D speaker driver. When this supply voltage drops below the proper level then under-voltage protection will be tripped. All protection statuses are available via register reads.

The Class-D output switching frequency is synchronous with the digital input audio sample rate to avoid left and right PWM frequency differences from beating in stereo applications. PWM Edge rate control and Spread Spectrum features are available if further EMI reduction is desired in the user’s system.

The interrupt request pin, IRQ, indicates a device error condition. The interrupt flag condition or conditions are selectable via I2C and include: thermal overload, Class-D over-current, VBAT level low, VBOOST level Low, and PLL out-of-lock conditions. The IRQ signal is active-high for an interrupt request and active-high during normal operation. This behavior can be changed by a register setting to tri-state the pin during normal operation to allow the IRQ pin to be tied in parallel with other active-low interrupt request pins on other devices in the system.

Stereo configuration can be achieved with two TAS2555 devices by using the ADR0_SCLK and ADR1_MISO pins to set different I2C addresses in I2C mode or the SCL_SSZ chip enable pin in SPI mode. Refer to the General I2C Operation or General SPI Operation sections for more details.

Functional Block Diagram

TAS2555 device_block_diagram_digital.gif

Feature Description

General I2C Operation

The TAS2555 device operates as an I2C slave over the IOVDD voltage range. It is adjustable to one of four I2C addresses. This allows multiple TAS2555 devices in a system to connect to the same I2C bus. The I2C pins are fail-safe. If the part has not power or is in shutdown the I2C pins will not have impact the I2C bus allowing it to remain useable.

To configure the TAS2555 for I2C operation set the SPI_SELECT pin to ground. The I2C address can then be set using pins ADR0_SCLK and ADR1_MSIO. The pins configure the two LSB bits of the following 7-bit binary address A6-A0 of 10011xx. This permits the I2C address of TAS2555 to be 0x4C(7bit) through 0x4F(7-bit). For example, if both ADR0_SCLK and ADR1_MSIO are connected to ground the I2C address for the TAS2555 would be 0x4C(7bit). This is equivalent to 0x98 (8-bit) for writing and 0x99 (8-bit) for reading.

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The corresponding pins on the TAS2555 for the two signals are SDA_MOSI and SCL_SSZ. The bus transfers data serially, one bit at a time. The address and data 8-bit bytes are transferred most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 19 shows a typical sequence.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bi-directional bus using a wired-AND connection.

Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Use pull-up resistors between 660 Ω and 4.7 kΩ. Do not allow the SDA and SCL voltages to exceed the device supply voltage, IOVDD.

TAS2555 i2c_seq_los492.gif Figure 19. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 19 shows a generic data transfer sequence.

Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for all registers. During multiple-byte read operations, the TAS2555 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges.

The TAS2555 supports sequential I2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.

Single-Byte Write

As shown in Figure 20, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C device address and the read/write bit, the TAS2555 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the device internal memory address being accessed. After receiving the register byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

TAS2555 sbw_trn_los492.gif Figure 20. Single-Byte Write Transfer

Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TAS2555 as shown in Figure 21. After receiving each data byte, the device responds with an acknowledge bit.

TAS2555 mbw_trn_los492.gif Figure 21. Multiple-Byte Write Transfer

Single-Byte Read

As shown in Figure 22, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a 0.

After receiving the TAS2555 address and the read/write bit, the device responds with an acknowledge bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit. The master device transmits another start condition followed by the TAS2555 address and the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TAS2555 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.

TAS2555 sbr_trn_los492.gif Figure 22. Single-Byte Read Transfer

Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the TAS2555 to the master device as shown in Figure 23. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

TAS2555 mbr_trn_los492.gif Figure 23. Multiple-Byte Read Transfer

General SPI Operation

The TAS2555 operates as an SPI slave over the IOVDD voltage range.

Class-D Edge Rate Control

The edge rate of the Class-D output is controllable via I2C register B0_P0_R6[2:0]. This allows users the ability to adjust the switching edge rate of the Class-D amplifier, trading off some efficiency for lower EMI. Table 1 lists the typical edge rates. The default edge rate of 14ns passes EMI testing. The default value is recommended but may be changed if requried.

Table 1. Class-D Edge Rate Control

DAC_EDGE BYTE:
DAC_EDGE[2:0]
tR AND tF
(TYPICAL)
01029 ns
01125 ns
10014 ns (default)
10113 ns
11012 ns
11111 ns

Battery Tracking AGC

The TAS2555 device monitors battery voltage and the audio signal to automatically decrease gain when the battery voltage is low and audio output power is high. This provides louder audio while preventing early shutdown at end-of-charge battery voltage levels. The battery tracking AGC starts to attenuate the signal once the voltage at the Class-D output exceeds VLIM for a given battery voltage (VBAT). If the Class-D output voltage is below the VLIM value, no attenuation occurs. If the Class-D output exceeds the VLIM value the AGC starts to attack the signal and reduce the gain until the output is reduced to VLIM. Once the signal returns below VLIM plus some hysteresis the gain reduction decays. The VLIM is constant above the user configurable inflection point. Below the inflection point the VLIM is reduced by a user configurable slope in relation to the battery voltage. The attack time, decay time, inflection point and VLIM/VBAT slope below the inflection point are user configurable. The parameters for the Battery Tracking AGC are part of the DSP core and can be set using thePurePath Console 3 Software TAS2555 Application software for the TAS2555 device part under the Device Control Tab. Below a VBAT level of 2.9 V, the boost will turn on to ensure correct operation but results in increased current consumption. The device is functional until the set brownout level is reached and the device shuts down. The minimum brownout voltage is 2.7 V.

TAS2555 SpeakerGuard_las898.gif Figure 24. VLIM versus Supply Voltage (VBAT)

Configurable Boost Current Limit (ILIM)

The TAS2555 device has a configurable boost current limit (ILIM). The default current limit is 3 A but this limit may be set lower based on selection of passive components connected to the boost. The TAS2555 device supports 4 different boost limits.

Table 2. Current Limit Settings

CURRENT LIMIT REGISTER
B0_P0_R43_D[1:0]
BOOST CURRENT LIMIT (ILIM)
(A)
001.5
012.0
102.5
113.0 (default)

Fault Protection

The TAS2555 device has several protection blocks to prevent damage. Those blocks including how to resume from a fault are presented in this section.

OverCurrent

The TAS2555 device has an integrated overcurrent protection that is enabled once the Class-D is powered up. A fault on the Class-D output causing a large current in the range of 3 A to 5 A triggers the overcurrent fault. Once the fault is detected the TAS2555 device disables the audio channel and power down the Class-D amplifier. When an over-current event occurs, a status flag at B0_P0_R104[7] is set. This register is sticky and the bit remains high for as long as it is not read, or the device is not reset. The overcurrent event can also be used to generate an interrupt if required. Refer to "IRQ and flags" section for more details. To re-enable the audio channel after a fault the Class-D the device must be hardware or software reset and the TAS2555 configuration must be re-loaded.

Analog Undervoltage

The TAS2555 device has an integrated undervoltage protection on the analog power supply lines AVDD and VBAT. The undervoltage limit fault is triggered when AVDD is less than 1.5 V or when VBAT is less than 2.4 V. Once the fault is detected the TAS2555 device will disable the audio channel and power down the Class-D amplifier. When an under-voltage event occurs, a status flag at B0_P0_R104[6] is set. This register is sticky and the bit will remain high for as long as it is not read, or the device is not reset. The undervoltage event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. To re-enable the audio channel after a fault the Class-D must be re-enabled by setting B0_P0_R5[7]=1. All other configurations are preserved and the audio channel will power up with the last configured settings.

Overtemperature

The TAS2555 device has an integrated overtemperature protection that is enabled once the Class-D is powered up. If the device internal junction temperature exceeds the safe operating region it will trigger the overtemperature fault. Once the fault is detected the TAS2555 device disables the audio channel and power down the Class-D amplifier. The device waits until the user reads the overtemperature flag in B0_P0_R104[4] to re-enable the Class-D amplifier if the junction temperature returns into a safe operating region. When an over-temperature event occurs, a status flag at B0_P0_R104[4] is set. This register is sticky and the bit will remain high for as long as it is not read, or the device is not reset. The overtemperature event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. The overtemperature automatic re-enable can be disabled by setting B0_P2_R9[2]=1. If the automatic re-enable is disabled, to re-enable the audio channel after the overtemperature fault the Class-D must be re-enabled by setting B0_P0_R5[7]=1. All other configurations are preserved and the audio channel will power up with the last configured settings.

Clocking Faults

The TAS2555 device has two clock error detection blocks. The first is on the Audio Serial Interfaces (ASI). If a clock error is detected on the ASI interfaces audio artifacts can occur at the Class-D output. When enabled the ASI clock error detection can mute the device and shutdown the Class-D and DSP core. The clock error detection block is enabled by setting register bit B0_P0_R44[1]=1. The ASI1 or ASI2 clocks can be routed to the block for detection using register B0_P0_R44[4]. Additionally, the clock error can be routed to an interrupt pin and the sticky bit at register B0_P0_R104[5] indicates the clock error occurred. The second clock error detection block can monitor the DAC, ADC, and PLL clocks. When a clock error is detected the output is soft-muted and the Class-D powered down. This clock error detection is enabled using register bit B0_P0_R44[0], can be routed to interrupt pin and is indicated in the sticky bit B0_P0_R104[2].

When a clocking error occurs the following sequence should be performed to restart the device.

  • Clear the clock error interrupts by reading the sticky flags at registers B0_P0_R104 and B0_P0_R108
  • Disable the clock error detection blocks by writing B0_P0_R44[7:0]=0x00 as the internal dividers will be stopped on error detection.
  • Shutdown by writing B0_P0_R4=0x00 and B0_P0_R5=0x00
  • Re-power appropriate devices in the same registers
  • Re-enable the clock error detection blocks in register B0_P0_R44

Brownout

The TAS2555 device has an integrated brownout system to shutdown the device when the battery voltage drops to an insufficient level. This user configurable level can be set under Device Control in the PurePath Console 3 Software TAS2555 Application. When brownout event occurs a status flag B0_P0_R104[3] is set. This register is sticky and the bit remains high for as long as it is not read, or the device is not reset. The brownout event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. Once the battery voltage drops below the defined threshold the following actions occur.

  • The audio playback is muted in a graceful soft-stepping manner
  • DSP, clock dividers, and analog blocks are powered down. B0_P0_R4[7:3]=00000 and B0_P0_R5[7:0]=0x00
  • Sticky bit B0_P0_R104[3] is set

Once the host is aware of the brownout it should write B0_P0_R4[0] =0 to put the TAS2555 device in software shutdown and enter low power mode. Once the battery supply is stable above the defined brownout threshold the host can re-enable the device using the Power Control Registers B0_P0_R4 and B0_P0_R5.

Spread Spectrum vs Synchronized

The Class-D switching frequency can be selected to work in two different modes of operations. This configuration must be done before powering up the audio channel. The first is a synchronized mode where the Class-D frequency is synchronized frequency to audio input sample rate. This is the default mode of operation and should be used in stereo applications to avoid inter-modulation beating of the Class-D frequency from multiple chips. The Class-D switching frequency in this mode can be configured as 384 kHz for 352.8 kHz. The 384 kHz frequency is the default mode of operation, and can be used for input signals running on clock rates of 48 kHz or its sub-multiples. For input signals running on clock rate of 44.1 kHz and its sub-multiples, the switching frequency can be selected as 352.8 kHz by setting B0_P2_R6[4]=1.

The second mode is spread-spectrum mode used to reduce wideband spectral content, improving EMI emissions radiated by the speaker. In this mode, the Class-D switching frequency varies +-5% about a 384 kHz center frequency. This mode can be configured by setting B0_P0_R40[0]=1 and B100_P0_R40[7]=0. Both these registers should be written before powering up the audio channel.

IRQs and Flags

Internal device flags such as overcurrent, under-voltage, etc can be routed as interrupts. The device has 4 interrupts that can be routed to any of the 10 GPIO pins. If more than one flag is assigned to the same interrupt the interrupt output is the logical OR-ing of all flags. If multiple flags are assigned to the same interrupt the host should then query the flags sticky register to determine which event triggered the interrupt. The 10 GPIO pins can be configured for any interrupt and can be configured using B0_P1_R61 thru B0_P1_R70.

Table 3. Interrupt Registers

Flag Name Flag DescriptionSticky Register Bit Register to Route Flag to Interrupt
Flag 1 Over CurrentB0_P0_R104[7] B0_P1_R108[6:4]
Flag 2 Under Voltage B0_P0_R104[6]B0_P1_R108[2:0]
Flag 3Clock Error Detection 1B0_P0_R104[5]B0_P1_R109[6:4]
Flag 4Over TemperatureB0_P0_R104[4]B0_P1_R109[2:0]
Flag 5BrownoutB0_P0_R104[3]B0_P1_R110[6:4]
Flag 6Clock Error Detection 2B0_P0_R104[2]B0_P1_R110[2:0]
Flag 7SAR CompleteB0_P0_R104[1]B0_P1_R111[6:4]

For example, to route the Brownout and Under Voltage flags to GPIO5 (Pin IRQ_GPIO5) the following register settings would be used. The flag Brownout would be routed to Interrupt 1 by setting B0_P1_R110[6:4]=001 and flag Under Voltage would be also routed to interrupt 1 by setting B0_P1_R108[2:0]=001. The pin IRQ_GPIO5 would be set to use interrupt 1 by setting B0_P1_R64[4:0]=0x07

Software Reset

The TAS2555 device internal logic must be initialized to a known condition for proper device function by doing a software reset. Performing software reset after a hardware reset is mandatory for reliable device boot up. To perform software reset write ‘1’ to B0_P0_R1_D0. After reset, all registers are initialized with default values as listed in the Register Map. After software reset is performed, no register read/write should be performed within 100us.

PurePath™ Console 3 Software TAS2555 Application

The TAS2555 device contains an integrated DSP processing engine for advance speaker protection. The advanced features and a significant portion of the device configuration is performed using this tool. The base software is called Pure Path Console 3 (PPC3). Once the software is downloaded and installed from the TI website, the TAS2555 application can be download from with-in the software. The datasheet refers to options that can be configured using the PPC3 software tool.

Device Functional Modes

Audio Digital I/O Interface

Audio data is transferred between the host processor and the TAS2555 device via the digital audio data serial interface, or audio bus. The audio bus on this device is flexible, including left or right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly.

The audio bus of the TAS2555 device can be configured for left or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Registers B0_P1_R1_D[4:3] and B0_P1_R2_D[4:3] for ASI1 and Registers B0_P1_R21_D[4:3] and B0_P1_R22_d[4:3] . In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.

The bit clock is used to clock in and clock out the digital audio data across the serial bus. This signal can be programmed to generate variable clock pulses by controlling the bit-clock multiply-divide factor in Registers 0x08 through 0x10. The number of bit-clock pulses in a frame may require adjustment to accommodate various word-lengths as well as to support the case when multiple TAS2555 devices may share the same audio bus.

The TAS2555 device also includes a feature to offset the position of start of data transfer with respect to the word-clock. This offset is in number of bit-clocks and is programmed in Register 0x06.

To place the DOUT line into a Hi-Z (3-state) condition during all bit clocks when valid data is not being sent, set Register B0_P1_R1_D[0] = 1 for ASI1 and Register B0_P1_R21[0] = 1. By combining this capability with the ability to program what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished. This enables the use of multiple devices on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode, the terminals associated with the interface are put into a Hi-Z output state.

Right-Justified Mode (RJF)

Audio Serial Interface 1 can be put into Right Justified Mode by programming B0_P1_R1_D[7:5] = 010 and B0_P1_R2_D[7:5] = 010 . Audio Serial Interface 2 can be put into Right Justified Mode by programmingB0_P1_R21_D[7:5] = 010 and B0_P1_R22_D[7:5] = 010. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

TAS2555 t_rt_jus_los585.gif Figure 25. Timing Diagram for Right-Justified Mode

For right-justified mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data.

Left-Justified Mode (LJF)

Audio Serial Interface 1 can be put into left-justified mode by programming B0_P1_R1_D[7:5] = 011 and B0_P1_R2_D[7:5] = 011 . Audio Serial Interface 2 can be put into left-justified mode by programming B0_P1_R21_D[7:5] = 011 and B0_P1_R22_D[7:5] = 011. In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

TAS2555 t_lft_jus_los585.gif Figure 26. Timing Diagram for Left-Justified Mode
TAS2555 t_lft_offset_los585.gif Figure 27. Timing Diagram for Light-Left Mode with Offset = 1
TAS2555 t_lft_inv_los585.gif Figure 28. Timing Diagram for Left-Justified Mode with Offset = 0 and Inverted Bit Clock

For left-justified mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data. Also, the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

I2S Mode

Audio Serial Interface 1 can be put into I2S Mode by programming B0_P1_R1_D[7:5] = 000 and B0_P1_R2_D[7:5] = 000 . Audio Serial Interface 2 can be put into I2S Mode by programming B0_P1_R21_D[7:5] = 000 and B0_P1_R22_D[7:5] = 000. In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

TAS2555 t_dia_los585.gif Figure 29. Timing Diagram for I2S Mode
TAS2555 t_dis_offset_los585.gif Figure 30. Timing Diagram for I2S Mode with Offset = 2
TAS2555 t_dis_inv_los585.gif Figure 31. Timing Diagram for I2S Mode with Offset = 0 and Inverted Bit Clock

For I2S mode, the number of bit-clocks per channel should be greater than or equal to the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

DSP Mode

Audio Serial Interface 1 can be put into DSP Mode by programming B0_P1_R1_D[7:5] = 001 and B0_P1_R2_D[7:5] = 001 . Audio Serial Interface 2 can be put into DSP Mode by programming B0_P1_R21_D[7:5] = 001 and B0_P1_R22_D[7:5] = 001. In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.

TAS2555 t_dsp_los585.gif Figure 32. Timing Diagram for DSP Mode
TAS2555 t_dsp_offset_los585.gif Figure 33. Timing Diagram for DSP Mode with Offset=1
TAS2555 t_dsp_inv_los585.gif Figure 34. Timing Diagram for DSP Mode with Offset=0 and Inverted Bit Clock

For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

TDM Mode

Time-division multiplexing (TDM) allows two or more devices to share a common DIN connection and a common DOUT connection. Using TDM mode, all devices transmit their DOUT data in user-specified sub-frames within one WCLK period. When one device transmits its DOUT information, the other devices place their DOUT terminals in a high impedance tri-state mode.

TDM mode is useable with I2S, LJF, RJF, and DSP interface modes. Refer to the respective sections for a description of how to set the TAS2555 device into those modes.

Use Register B0_P1_R3 for ASI1 and B0_P1_R23 for ASI2 to set the clock cycle offset from WCLK to the MSB. Each data bit is valid on the falling edge of the bit clock. Set Register B0_P1_R1_D[0] = 1 for ASI1 and B0_P1_R21_D[0] = 1 to force DOUT into tri-state when it is not transmitting data. This allows DOUT terminals from multiple TAS2555 devices to share a common wire to the host.

TAS2555 t_dis_offset_los585.gif Figure 35. Timing Diagram for I2S in TDM Mode with Offset=2

For TDM mode, the number of bit-clocks per frame should be less than the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

Device Digital Processing Modes

The TAS2555 DSP can be initialized into one of three modes.

ROM Mode 1

ROM mode 1 provides the quickest initialization from the TAS2555 initial power up and is the lowest power mode. This mode can be used to play a known power up audio sequence before the rest of the audio system software is loaded. The mode provides fault protection, brownout protection volume control, and class-H controller. With minimal additional configuration the EQ and Battery Guard can be enabled. The speaker protection algorithm is not running in this mode and the I/V sense ADC are powered down to minimize power consumption. The PLL can be disabled for even lower power consumption if the MCLK supplied is at least 12.288MHz for any fs which is multiple or sub-multiple of 48kHz, or 11.2896MHz for fs of 44.1kHz. This mode is set by writing B)_P0_R34[7:0]=0x21 before powering up the DSP B0_P0_R4[7]. This mode should be used to characterize the electrical performance on the TAS2555 device without any influence from the protection algorithm present in other modes.

TAS2555 Rom-Mode1.gif Figure 36. ROM Mode 1 Processing Block Diagram

ROM Mode 2

ROM mode 2 is similar to ROM mode 1 except the I/V sense ADCs are powered up and the data is routed back on the L/R return channels of the ASI port. This mode can be used to return the I/V data to the host and perform alternate computations on the speaker I/V measurements. This mode is set by writing B0_P0_R34[7:0]=0x22 before powering up the DSP B0_P0_R4[7].

TAS2555 Rom_Mode2.gif Figure 37. ROM Mode 1 Processing Block Diagram

SmartAmp Mode

SmartAmp Mode is used to run the TI SmartAmp algorithm on the built in DSP. This mode involves loading larger output files generated from the PurePath Console 3 Software TAS2555 Application. The generated files contain the speaker models, equalization, and additional configuration parameters in a format to load over the I2C or SPI interface. TI's SmartAmp provides Thermal and Excursion protection using initial speaker models and the current and voltage feedback to determine exact coil temperature and update the initial model due to variations in speaker and ambient conditions. More information about this mode can be found in the PurePath Console 3 Software TAS2555 Application.

Low Power Sleep Mode

The device has a low power sleep mode option to reduce the power consumption on analog supplies (AVDD and VBAT). There are two lower power modes and the choice depends on AVDD supply. First, if the AVDD supply does not drop below the minimum specified voltage, the lowest power mode can be activated by performing a software reset B0_P0_R1[0]=1, waiting 100us and then writing shutdown POR blocks B0_P0_R121[7]=1. To exit the low power sleep mode write B0_P0_R121[7]=0 to power up the Avdd and Vbat POR. The part ideally can be placed in low power mode by only shutting down the POR blocks. However, due to non-default configurations TI recommends the software reset.

If the AVDD POR must remain enabled an alternate low power mode should be used. To enable the second low power mode write B0_P0_R4[7:0]=0 and B0_P0_R5[7:0]=0.

Programming

Code Loading and CRC check

The TI SmartAmp software is loaded into program ram(PRAM) through writes to mapped memory registers. The encrypted binary software is downloaded and decoded on chip. Therefore read-back of the PRAM is disabled. However a 8 bit CRC checksum is provided to the customer to verify the code was correctly written to PRAM error-free. Once the software download is complete the calculated 8-bit CRC checksum can be read from B0_P0_R32. If this value matches the checksum supplied with the program the load to PRAM was successful. If new PRAM code is loaded the TAS2555 device should first be software or hardware reset to reset the CRC checksum register to obtain a proper checksum from the new code to be loaded.

The following is an example script used to load the DSP software and verify the CRC checksum.

##############################################################################################This script is a demo for downloading the PRAM code and checking CRC checksumi i2cstd#mclk expected is 24.576 MHz#configuring device registers for 8 ohm speaker load########################### DEVICE INIT SEQ START##############################################w 98 00 00 #Page-0w 98 7f 00 #Book-0w 98 01 01 #Software reset d 1 # wait 100us time for OTP-One Time Programmable memory values to be transferred to device ##### INIT SECTION STARTw 98 7f 64 # book 100w 98 46 01 # IRAM bootw 98 7f 00 # book 0##### INIT SECTION END##### DSP PROG SETTING STARTw 98 7f 64w 98 00 01#add writes for download to PRAM herew 98 00 00w 98 7f 00##### DSP PROG SETTING END########################### DEVICE INIT SEQ END ###############################################r 98 20 1 # reading the CRC checksum for the PRAM download , if read = CRC checksum provided to customer => PRAM download success ################### CHANNEL POWER UP ####################################################w 98 05 A3 # Power up Analog Blocksw 98 04 B8 # Power up DSP and clock dividersw 98 07 00 # Unmute Analog Blocksw 98 7f 64 # switch to book100w 98 07 00 # Soft stepped unmute of audio playback################################################################################################# DSP coeff update START# d 1# DSP filter coefficient update if required##### DSP coeff update END############device powered up and running############################# CHANNEL POWER DOWN ####################################################w 98 07 01 # Soft stepped mute of audio playbackd 10 # wait for DSP to mute classD after soft step down of audio# instead of delay alternatively status flag B120_P15_R120_R121_R122_R123 polling can be done and wait till R122_D0 = '1'.w 98 7f 00 # switch to book0w 98 07 03 # Mute Analog Blocksw 98 04 20 # Power down DSP and clock dividers (except Ndivider)w 98 05 00 # Power down Analog Blocks w 98 00 00 # NOP w 98 04 00 # Power down Ndivider ##############################################################################################optional(ending the script in B0_P0)w 98 00 00 # page 0w 98 7f 00 # book 0#############################################################################################

Device Power Up, Power Down, Mute and Un-mute Sequence

The following code example provide the correct sequence to power up the device, unmute and mute, and provide a clean power-down. The PurePath Console 3 Software TAS2555 Application software will create output files with these commands. The following is a example of powering up the part in DSP Mode 2 with proper sequencing.

Example script (ROM Mode 2):#############################################################################################i i2cstd#mclk expected is 24.576 MHz#configuring device registers for 8 ohm speaker load########################### DEVICE INIT SEQ START##############################################w 98 00 00 #Page-0w 98 7f 00 #Book-0w 98 01 01 #Software reset d 1 # wait 100us time for OTP-One Time Programmable memory values to be transferred to device ##### DSP PROG SETTING STARTw 98 22 22 # use default coefficients and operate DSP in rom mode 2##### DSP PROG SETTING END########################### DEVICE INIT SEQ END ################################################################## CHANNEL POWER UP ####################################################w 98 05 A3 # Power up Analog Blocksw 98 04 B8 # Power up DSP and clock dividersw 98 07 00 # Unmute Analog Blocksw 98 7f 64 # switch to book100w 98 07 00 # Soft stepped unmute of audio playback################################################################################################# DSP coeff update START# d 1# DSP filter coefficient update if required##### DSP coeff update ENDb ############device powered up and running############################# CHANNEL POWER DOWN ####################################################w 98 07 01 # Soft stepped mute of audio playbackd 10 # wait for DSP to mute classD after soft step down of audio# instead of delay alternatively status flag B120_P15_R120_R121_R122_R123 polling can be done and wait till R122_D0 = '1'.w 98 7f 00 # switch to book0w 98 07 03 # Mute Analog Blocksw 98 04 20 # Power down DSP and clock dividers (except Ndivider)w 98 05 00 # Power down Analog Blocks w 98 00 00 # NOP w 98 04 00 # Power down Ndivider ##############################################################################################optional(ending the script in B0_P0)w 98 00 00 # page 0w 98 7f 00 # book 0#############################################################################################