CDCLVC1103
- High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, 1:12 LVCMOS Clock Buffer Family
- Very Low Pin-to-Pin Skew < 50 ps
- Very Low Additive Jitter < 100 fs
- Supply Voltage: 3.3 V or 2.5 V
- fmax = 250 MHz for 3.3 V
fmax = 180 MHz for 2.5 V - Operating Temperature Range: –40°C to 85°C
- Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP Package (All Pin-Compatible)
The CDCLVC11xx is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments.
The entire family is designed with a modular approach in mind. It is intended to round up TIs series of LVCMOS clock generators.
Seven different fan-out variations, 1:2 to 1:12, are available. All of the devices are pin-compatible to each other for easy handling.
All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.
The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low.
The CDCLVC11xx family operates in a 2.5-V and
3.3-V environment and are characterized for operation from –40°C to 85°C.
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Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family datasheet (Rev. B) | PDF | HTML | 24 Feb 2017 |
Application note | How to Apply 1.8-V Signals to 3.3-V CDCLVC11xx Fanout Clock Buffer | 30 Nov 2010 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
CDCLVC1104EVM — CDCLVC1104 Evaluation Module
CDCLVC1102/03/04/06/08/10/12 IBIS Model (Rev. B)
CLOCK-TREE-ARCHITECT — Clock tree architect programming software
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
---|---|---|
TSSOP (PW) | 8 | View options |
Ordering & quality
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