ZHCSJK9H June   2001  – October 2015 TPS54610

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      在 350 kHz 时的效率
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Lockout (UVLO)
      2. 8.3.2  Slow Start/Enable (SS/ENA)
      3. 8.3.3  VBIAS Regulator (VBIAS)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Oscillator and PWM Ramp
      6. 8.3.6  Error Amplifier
      7. 8.3.7  PWM Control
      8. 8.3.8  Dead-Time Control and MOSFET Drivers
      9. 8.3.9  Overcurrent Protection
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Power-Good (PWRGD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 Switching Frequency Selection/Synchronization
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High Frequency Switching Regulator Using Ceramic Output Capacitors
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Component Selection
          2. 9.2.1.2.2 Input Filter
          3. 9.2.1.2.3 Feedback Circuit
          4. 9.2.1.2.4 Operating Frequency
          5. 9.2.1.2.5 Output Filter
        3. 9.2.1.3 Application Curves
      2. 9.2.2 High Frequency Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 相关直流/直流产品
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

6 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP With Exposed Thermal Pad
Top View
TPS54610 po__lvs398.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 1 G Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Connect PowerPAD™ to AGND.
BOOT 5 S Bootstrap output. 0.022-μF to 0.1-μF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver.
COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE
PGND 15-19 G Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative pins of the input and output capacitors. A single point connection to AGND is recommended.
PH 6-14 O Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD 4 O Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or the internal shutdown signal is active.
RT 28 I Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA 26 I/O Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time.
SYNC 27 I/O Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin.
VBIAS 25 S Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low-ESR 0.1-μF to 1.0-μF ceramic capacitor.
VIN 20-24 I Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low-ESR 10-μF ceramic capacitor.
VSENSE 2 I Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
(1) I = Input, O = Output, S = Supply, G = Ground Return