SWRU437B September   2015  – June 2020 WL1801MOD , WL1805MOD , WL1807MOD , WL1831MOD , WL1835MOD , WL1837MOD

 

  1.   WiLink Module Hardware Integration Guide
    1.     Trademarks
    2. 1  Module Variant Table
      1. 1.1 WiLink WLAN Antenna Configuration
        1. 1.1.1 Single-Input Single-Output (SISO)
        2. 1.1.2 Multiple-Input Multiple-Output (MIMO)/Maximum Ratio Combining (MRC)
    3. 2  Critical Connections
    4. 3  Power Supply
      1. 3.1 Power Up/Shutdown Sequence
        1. 3.1.1 Power Up
        2. 3.1.2 Shutdown
      2. 3.2 Power Sequencing
    5. 4  Clocks
      1. 4.1 Slow Clock
      2. 4.2 Fast Clock
    6. 5  Current Consumption
      1. 5.1 Performance Parameters - Typical
    7. 6  Antenna
    8. 7  Ground Connections
    9. 8  Layout
    10. 9  Hardware Troubleshoot
      1. 9.1 System Requirements
      2. 9.2 Power Rails
      3. 9.3 Critcal Supplies
      4. 9.4 Sense on Reset
      5. 9.5 WLAN
        1. 9.5.1 WLAN Host Interface (SDIO)
        2. 9.5.2 WLAN IRQ Operation (SDIO Out-of-Band Interrupt)
      6. 9.6 Bluetooth and Bluetooth Low Energy
        1. 9.6.1 Bluetooth UART HCI Interface
        2. 9.6.2 Bluetooth PCM
      7. 9.7 Reserved Pins
      8. 9.8 Debug
    11. 10 WiFi_Zigbee Coex
    12. 11 References
  2.   Revision History

9.5.1 WLAN Host Interface (SDIO)

The SDIO is the host interface for WLAN. The interface between the host and the WiLink module uses an SDIO interface and supports a maximum clock rate of 52 MHz.

The device SDIO also supports the following features of the SDIO V3 specification:

  • 4-bit data bus
  • Synchronous and asynchronous in-band interrupt
  • Default and high-speed (HS, 52 MHz) timing
  • Sleep and wake commands
  • The WLAN subsystem is controlled via an SDIO interface. The WLAN acts as a slave with the processor as host. The host should generate the SDIO clock and read/write from the WLAN interface.
  • Verify that the SDIO bus pins are connected to the host. These pins include:

    Table 7. SDIO Interface Lines

    Pin Number Name Type Description
    6 SDIO_CMD I/O SDIO command line. This is a bidirectional line. The host sends commands and the WLAN responds to these commands.
    8 SDIO_CLK I SDIO clock input line. This line is generated by the host.
    10 SDIO_D0 I/O SDIO data 0 line. This is the primary data line used in both 1-bit and 4-bit SDIO mode. This is a bidirectional line.
    11 SDIO_D1 I/O SDIO data 1 line. This is one of four data lines. This line is used only in 4-bit mode. This is a bidirectional line.
    12 SDIO_D2 I/O SDIO data 2 line. This is one of four data lines. This line is used only in 4-bit mode. This is a bidirectional line.
    13 SDIO_D3 I/O SDIO data 3 line. This is one of four data lines. This line is used only in 4- bit mode. This is a bidirectional line.
    14 WLAN_IRQ O Generates interrupt from the WLAN chip toward the HOST. It is used to signal the HOST on many events like received data from the WLAN media is ready at the firmware (WLAN Chip) queue, the last Tx frame that was transmitted, all kind of asynchronous messages (evens), and so on.
    40 WLAN_EN I WLAN enable signal, should be "1" in order enable the WLAN operation, once the WLAN enable signal is "0" the WLAN part of the chip is reset in a way that the firmware has to be loaded again after enabling the WLAN.
  • Host must provide PU using a 10-K resistor for all non-CLK SDIO signals.
  • In order to follow the wakeup/shutdown requirements, the WL_EN (pin number 40) should be connected to host GPIO. Must be pulled high for WLAN operation. This GPIO should have internal pull-up allowing the WiLink pin to remain high on host suspend. In order to enable WOW feature, a pull up on the line is required during HOST shutdown.
  • IRQ_WL should be connected to host GPIO. This GPIO should be able to wake the host from suspend, therefore it's better to always connect the pin (number 14) to the always on domain of the Host. The IRQ_WL pin serves as interrupt generation from WiLink to the host.

    • NOTE

    It is recommended to connect the SDIO directly to the 1.8 V SDIO interface on the host side. In case Level Shifter is inevitable, see Level Shifting WL18xx I/Os Application Report (SWRA448).