SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System

In a cascaded system, the FRC and chirp timing engines of the constituent chips are operated in synchronously. The master chip FRC generates the Dig Sync signal. Dig Sync is routed out of the master and fed to the slaves as well as back to the master to match the skew between master and slave chips. As illustrated in Figure 7 (2 chip cascade example), the Dig Sync is synchronized and used to ungated the clocks to all the RX ADC and chirp timing engines in the master and slaves, thereby ensuring timing alignment across chips. It also ensures that the processor firmware in the master and slaves run in (within 5 ns to 10 ns uncertainty). PCB routing of the Dig Sync signal should be delay matched for best alignment between master and slave chips.

fig7a.pngFigure 6. Frame (Burst) Timing Generation in Two Chip Cascade Example