SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

3.3 40 MHz (System) Reference Clock Connectivity

In the case when the Master chip sources the reference clock for the other Slave devices, the OSC_CLKOUT [A14] pin of the Master is used. OSC_CLKOUT feeds into the CLKP [E14] pin of the Slave chips. The OSC_CLKOUT signal is an approximately 1.3 V to ground square wave output. It can be dc-coupled or ac-coupled to the CLKP pin of Slave chip. The max input level at CLKP is 1.8 V when dc-coupled and 1.2 Vpp when ac-coupled.

When more than two chips are cascaded, it is recommended to use a clock fan-out buffer to generate the clocks for Slave devices.