SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

2.2 Digital Frame Sync

In a cascaded system, it is necessary to synchronize the RX ADC sampling windows between all chips. Frame Sync, described in this section, ensures coherence of ADC samples from all the chips and alignment of the chirp timing signals across the constituent chips.

Note that “Frame (Burst)” in this section refers to frames (as defined in AWR_FRAME_CONF_SB) and bursts (as defined in AWR_ADVANCED_FRAME_CONF_SB).