SNLU300A January   2023  – February 2023 DS160PR1601 , DS320PR1601

 

  1.   DS320PR1601RSC-EVM Evaluation Module (EVM)
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  4. 2Description
    1. 2.1 DS320PR1601 5-Level I/O Control Inputs
    2. 2.2 DS320PR1601 Modes of Operation
    3. 2.3 DS320PR1601 SMBus / I2C Register Control Interface
    4. 2.4 DS320PR1601 Channel Mapping
    5. 2.5 DS320PR1601 EVM Controls
    6. 2.6 Quick-Start Guide
  5. 3Schematics
  6. 4Board Layout
  7. 5Bill of Materials
  8. 6References
  9. 7Revision History

DS320PR1601 SMBus / I2C Register Control Interface

The DS320PR1601 internal registers can be accessed through standard SMBus protocol. The DS320PR1601 features eight banks of channels, A_Bank 0 (Channels 0–3) and A_Bank 1 (Channels 4–7), A_Bank 0 (Channels 8-11), A_Bank 1 (Channels 12-15), B_Bank 0 (Channels 0–3) and B_Bank 1 (Channels 4–7), B_Bank 0 (Channels 8-11), B_Bank 1 (Channels 12-15) each featuring a separate register set and requiring a unique SMBus target address. The SMBus target address pairs (one for each channel bank) are determined at power up based on the configuration of the x_ADDR1_x and x_ADDR0_x pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.

There are 16 unique SMBus target address pairs (one address for each channel bank) that can be assigned to the device by placing external resistor straps on the x_ADDR1_x and x_ADDR0_x pins as listed in Table 2-3.

Table 2-3 DS320PR1601 SMBus Address Map

x_ADDR1_x Pin Level

x_ADDR0_x Pin LevelA/B Bank 0:
7-Bit Address [HEX]
A/B Bank 1:
7-Bit Address [HEX]
L0L00x180x19
L0L10x1A0x1B
L0L20x1C0x1D
L0L30x1E0x1F
L1L00x200x21
L1L10x220x23
L1L20x240x25
L1L30x260x27
L2L00x280x29
L2L10x2A0x2B
L2L20x2C0x2D
L2L30x2E0x2F
L3L00x300x31
L3L10x320x33
L3L20x340x35
L3L30x360x37