SLVUC68 September   2021 TPSM5601R5H

 

  1.   Trademarks
  2. 1EVM Setup
  3. 2EVM Connectors and Test Points
  4. 3EVM Parameters
    1. 3.1 Maximum Output Current
    2. 3.2 Maximum VIN and VOUT Configurations
    3. 3.3 Switching Node Behavior
  5. 4Typical Performance
    1. 4.1 Typical Characteristics (VIN = 12 V)
    2. 4.2 Typical Characteristics (VIN = 24 V)
    3. 4.3 Typical Characteristics (VIN = 36 V)
    4. 4.4 Typical Characteristics (VIN = 48 V)
  6. 5Feature Description
    1. 5.1 Enable Pin (EN)
    2. 5.2 Power-Good Pin (PGOOD)
    3. 5.3 System Loop Stability
  7. 6Layout
    1. 6.1 PCB Layout
  8. 7Schematic
  9. 8Bill of Materials (BOM)
  10.   Device Support
    1.     Related Documentation
    2. 9.1 Support Resources

3.3 Switching Node Behavior

The voltage on the switch node switches from the input voltage to the negative output voltage in an inverting topology. During start-up, VIN rises to achieve the set input voltage, then the device begins switching, which causes the VOUT to start ramping down after the enable pin voltage exceeds its threshold and VIN exceeds its UVLO threshold. As VOUT continues to ramp down, the switch node low-level follows VOUT downward. Figure 3-2 displays a typical behavior of the switch node at start-up.

Figure 3-2 Switch Node Voltage During Start-Up