SLVUB77A July 2017 – October 2021 TPS54336A
2.10 Powering Down
Figure 2-13 and Figure 2-14 show the start-up waveforms for the TPS54336AEVM-010. In Figure 2-13, the output voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R1 and R2 resistor divider network. In Figure 2-14, the output is inhibited by using a jumper at JP1 to tie EN to GND. The input voltage for these plots is 24 V and the load is 5 Ω.
Figure 2-13 TPS54336AEVM-010 Shut-down Relative to VIN
Figure 2-14 TPS54336AEVM-010 Shut-down Relative to EN