SLVUB77A July   2017  – October 2021 TPS54336A

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Set Point
      2. 1.3.2 Adjustable UVLO
      3. 1.3.3 Adjustable Slow Start
  3. 2Test Setup and Results
    1. 2.1  Input/Output Connections
    2. 2.2  Efficiency
    3. 2.3  Output Voltage Load Regulation
    4. 2.4  Output Voltage Line Regulation
    5. 2.5  Load Transients
    6. 2.6  Loop Characteristics
    7. 2.7  Output Voltage Ripple
    8. 2.8  Input Voltage Ripple
    9. 2.9  Powering Up
    10. 2.10 Powering Down
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

Powering Up

Figure 2-11 and Figure 2-12 show the start-up waveforms for the TPS54336AEVM-010. In Figure 2-11, the output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1and R2 resistor divider network. In Figure 2-12, the input voltage is initially applied and the output is inhibited by using a jumper at JP1 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set value of 5 V. The input voltage for these plots is 24 V and the load is 5 Ω.

GUID-B77D1702-33D6-4F86-A8A4-C700140F9A9B-low.gifFigure 2-11 TPS54336AEVM-010 Start-Up Relative to VIN
GUID-C15C05D2-A528-49D0-B022-087950DBB480-low.gifFigure 2-12 TPS54336AEVM-010 Start-up Relative to Enable