SLVA528D September   2012  – August 2021 TPS65381-Q1 , TPS65381A-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Product Overview
    1. 2.1 Safety Functions and Diagnostics Overview
    2. 2.2 Target Applications
    3. 2.3 Product Safety Constraints
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
  5. 4TPS65381x-Q1 Product Architecture for Management of Random Faults
    1. 4.1 Device Operating States
    2.     Device Operating States (continued)
    3. 4.2 NRES (MCU Reset) Driver and ENDRV (SAFING Path Enable) Driver
  6. 5TPS65381x-Q1 Architecture Safety Mechanisms and Assumptions of Use
    1. 5.1 Power Supply
    2. 5.2 Regulated Supplies
      1. 5.2.1 VDD6 Buck Switch-Mode Supply
      2. 5.2.2 VDD5 Linear Supply
      3. 5.2.3 VDD3/5 Linear Supply
      4. 5.2.4 VDD1 Linear Supply
      5. 5.2.5 VSOUT1 Linear Supply
      6. 5.2.6 Charge Pump
    3. 5.3 Diagnostic, Monitoring, and Protection Functions
      1. 5.3.1 External MCU Fault Detection and Management
        1. 5.3.1.1 External MCU Error Signal Monitor (MCU ESM)
        2. 5.3.1.2 Watchdog Timer
      2. 5.3.2 Voltage Monitor (VMON)
      3. 5.3.3 Loss-of-Clock Monitor (LCMON)
      4. 5.3.4 Junction Temperature Monitoring and Current Limiting
      5. 5.3.5 Analog and Digital MUX (AMUX and DMUX) and Diagnostic Output Pin (DIAG_OUT)
      6. 5.3.6 Analog Built-In Self-Test (ABIST)
      7. 5.3.7 Logic Built-In Self-Test (LBIST)
      8. 5.3.8 Device Configuration Register Protection
  7. 6Application Diagrams
    1. 6.1 TPS65381x-Q1 With TMS570
    2. 6.2 TPS65381x-Q1 With C2000
    3. 6.3 TPS65381x-Q1 With TMS470
  8. 7TPS65381x-Q1 as Safety Element out of Context (SEooC)
    1. 7.1 TPS65381x-Q1 Used in an EV/HEV Inverter System
    2. 7.2 SPI Note
  9. 8Revision History

Device Operating States (continued)

GUID-BD60ADC1-B95F-49D4-B165-0F0801939B8B-low.gif
(1) RESET State: SPI, Watchdog and MCU ESM are in reset; see the data sheet for conditions that prevent the wake up from the STANDBY state to the RESET state.
(2) DIAGNOSTIC State: BIST (LBIST with ABIST) is initiated on the transition into the DIAGNOSTIC state. See the data sheet for options to disable automatic BIST run, the DIAGNOSTIC state time-out and diagnostics the MCU may perform on safety functions. WD_FAIL_CNT reinitializes to 5 on transition into the DIAGNOSTIC state.
(3) ACTIVE State: WD_FAIL_CNT reinitializes to 5 during transition into the ACTIVE state. During the ACTIVE state the MCU may perform diagnostics of some safety functions, see the data sheet for more details.
(4) SAFE State: DEV_ERR_CNT[3:0] increments on any transition to the SAFE state. See the data sheet for details on SAFE state time-out.
(5) The ENDRV pin level is dependent on the ENABLE_DRV bit, WD_FAIL_CNT[2:0] counter value, and VDDx_OV as shown in Figure 4-2 in the DIAGNOSTIC and ACTIVE states.
(6) The VDD5 and VSOUT1 regulators may be enabled or disabled in the DIAGNOSTIC, ACTIVE, and SAFE states.
Figure 4-1 Device Controller State Diagram