SLUAAH1 December   2021 UCC24624

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 LLC Resonant Converter
    2. 1.2 Synchronous Rectification (SR)
      1. 1.2.1 Diode Rectification and Synchronous Rectification
      2. 1.2.2 Power Loss for Synchronous Rectification
      3. 1.2.3 UCC24624 Introduction
  3. 2Configurations of Secondary Rectifier Circuit using UCC24624
    1. 2.1 Typical Configuration
    2. 2.2 Single SR Controller with Paralleled MOSFETs Configuration
    3. 2.3 Dual SR Controllers with Paralleled MOSFETs Configuration
    4. 2.4 Multi SR Controllers with Matrix Transformer Configuration
  4. 3Summary
  5. 4References

2.2 Single SR Controller with Paralleled MOSFETs Configuration

In higher power level applications, a number of MOSFETs can be paralleled to achieve lower on-state resistance and reduce conduction loss as shown in Figure 2-2. Also, the RDS(ON) has a positive temperature coefficient so the FETs will automatically share current, facilitating optimal thermal distribution among the SR devices. This improves the thermal management.

GUID-20211217-SS0I-BZST-0Z6P-XFWJV3WNCBJ9-low.pngFigure 2-2 Single UCC24624 with Parallel MOSFETs Application Schematic

To minimize the size of the converter and decrease output ripple voltage for low-voltage applications, designers often increase the switching frequency to reduce the size of the output inductor and capacitor. If multiple FETs are in parallel, increased switching frequency increases the gate drive losses which might make UCC24624 overheat. According to Equation 9, the gate driver losses greatly increases as shown in Equation 11.

Equation 10. PGATE ↑↑=2 * Qg* Vgs* fsw↑* N ↑