SLAU150A December   2004  – October 2021 ADS7881 , ADS7891

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Analog Interface
      1. 1.2.1 Signal Conditioning
      2. 1.2.2 Reference
    3. 1.3 Digital Interface
    4. 1.4 Power Supplies
  3. 2Using the EVM
  4. 3ADS78x1EVM Bill of Materials
  5. 4ADS78x1EVM Layout
  6. 5ADS78x1EVM Schematics
  7. 6Revision History

Digital Interface

The ADS78x1EVM is designed for easy interfacing to multiple platforms. Samtec part numbers SSW-110-22-F-D-VS-K, TSM-110-01-T-DV-P, SSW-116-22-S-D-VS, and TSM-116-01-T-D-V-P provide a convenient dual row header and socket combination at P1, P2, P3, and J3. Consult Samtec at www.samtec.com or 1-800-SAMTEC-9 for a variety of mating connector options.

Connectors P1, P2, and P3 allows the user to plug the EVM into the 5-6k interface card to interface directly with the TMS320C5000 and TMS320C6000 series of DSP. Table 1-4 lists the connector pin out.

Table 1-4 Pin Out for Parallel Control Connector P2
Connector.Pin(1) Signal Description
P2.1 DC_CS Daughter card board select pin
P2.3
P2.5
P2.7 A0 Address line from processor
P2.9 A1 Address line from processor
P2.11 A2 Address line from processor
P2.13
P2.15
P2.17
P2.19 BUSY Busy signal from converter. W4 must be shorted.
All even-numbered pins of P2 are tied to DGND.

Read (RD), conversion start (CONVST) and reset (RESET) signals to the converter can be assigned to two different addresses in memory via jumper settings. The jumper settings allow up to two ADS78x1EVMs to be stacked into processor memory. See Table 1-5 for jumper settings. The evaluation module does not allow the chip-select (CS) line of the converter to be assigned to different memory locations. Instead, ground or wire the CS line to an appropriate signal of the user processor.

Table 1-5 Jumper Settings
Reference
Designator
Description Pins
1–2 2–3
W1 Short U8 pin 14 to power-down or reset signal Installed(1)
Short U8 pin 13 to power-down or reset signal Installed
W2 Short U8 pin 12 to CONVST signal Installed(1)
Short U8 pin 11 to CONVST signal Installed
W3 Short U8 pin 10 to RD signal Installed(1)
Short U8 pin 8 to RD signal Installed
W4 Short inverted BUSY to INTC Installed(1)
Short BUSY to INTC Installed
W5 Short +5VD to +BVDD Installed(1)
Short +3.3VD to +BVDD Installed
Factory-set condition.

The data bus is available at connector P3. Table 1-6 lists the pin out information. This EVM supports two devices but the connector signals names are based on the ADS7981, which is the higher-resolution device. Depending on which device is being evaluated, care must be taken when connecting the EVM to a host processor.

Table 1-6 Data Bus Connector P3
Connector.Pin(1) Signal Name Description
ADS7881 ADS7891
P3.1 B_DB0 Not connected Buffered data bit 0 (LSB)
P3.3 B_DB1 Not connected Buffered data bit 1
P3.5 B_DB2 Buffered data bit 0 (LSB) Buffered data bit 2
P3.7 B_DB3 Buffered data Bit 1 Buffered data bit 3
P3.9 B_DB4 Buffered data bit 2 Buffered data bit 4
P3.11 B_DB5 Buffered data bit 3 Buffered data bit 5
P3.13 B_DB6 Buffered data bit 4 Buffered data bit 6
P3.15 B_DB7 Buffered data bit 5 Buffered data bit 7
P3.17 B_DB8 Buffered data bit 6 Buffered data bit 8
P3.19 B_DB9 Buffered data bit 7 Buffered data bit 9
P3.21 B_DB10 Buffered data bit 8 Buffered data bit 10
P3.23 B_DB11 Buffered data bit 9 Buffered data bit 11
P3.25 B_DB12 Buffered data bit 10 Buffered data bit 12
P3.27 B_DB13 Buffered data bit 11 (MSB) Buffered data bit 13 (MSB)
P3.29 Not connected Not connected Not connected
P3.31 Not connected Not connected Not connected
All even-numbered pins of P3 are tied to DGND.

As described in Table 1-7, this evaluation module provides direct access all the analog-to-digital converter control signals via connector J3.

Table 1-7 Pin Out for Converter Control Connector J3
Connector.Pin(1) Signal Description
J3.1 CS Chip-select pin. Active low.
J3.3 RD Read pin. Active low.
J3.5 CONVST Convert start pin. Active low.
J3.7 BYTE BYTE mode pin. Used for 8-bit buses.
J3.9 PWD/RST Active low input, acts as device power down or device reset signal.
J3.11 A_PDWN Nap mode enable, active low.
J3.13 BUSY Converter status output. High when a conversion is in progress.
All even-numbered pins of J3 are tied to DGND.