The CD74HC4094 is an example of a device that does not have guaranteed output levels upon power-up. Before a valid clock edge, thresholds within the device can cause the internal logic chains to product high or low signals. This effect can vary with voltage, temperature, manufacturing lot, and more. As a result, the outputs Q_n will be determined by unpredictable power-up states determined by these internal thresholds and should not be considered valid logic signals. However, once a valid clock edge has occurred, the outputs behave normally according to the truth table in the datasheet. For this particular device, 8 clock edges are required to shift the unknown data out of the device and ensure that all Q_n outputs are valid.

Another important consideration is the rise of the CLK signal simultaneously with V_CC. Although the clock signal will be seen as an appropriate edge on an oscilloscope, the device may not consider it a valid clock. As V_CC rises, the V_IH threshold of the clock signal also rises. If the two rise simultaneously, the clock signal may or may not cross the appropriate thresholds required to be considered valid. Capacitance within the circuit will also cause subtle and unpredictable differences in the timing of CLK and V_CC. Therefore, it is not recommended to produce a clock edge until V_CC has risen to a recommended level as specified in the device datasheet.

There are several methods that designers can use to prevent unwanted signals at power-up from affecting their systems.

Some devices come with input pins designed to ensure a specific state upon power up. For example, an alternative to the CD74HC4094 is the CD74HC299, which contains a Master Reset ( MR) pin, which sets all outputs low when the pin is pulled low. The outputs will be set low regardless of the state of the clock pulse (see the truth table in the datasheet). Other devices, such as the SN74HC74, have clear ( CLR or CLR) and preset ( PRE or PRE) pins. When active, the clear pins set the outputs low, and the preset pins set the outputs high, regardless of CLK. The polarities of the clear and preset pins vary among different parts, and it is typically not recommended to activate both of them at the same time (nonstable configuration). The truth table in the device datasheet specifies which configurations are not recommended.

The example in Figure 2-1 shows a configuration where the user wants an initial high output at Q. According to the truth table, this requires a high CLR and a low PRE. Use pullup resistors to connect the inputs to the appropriate levels. After power-up, the truth table says that PRE must then be pulled high to allow Data and CLK to control the output. The pullup resistor must be sized such that the device driving PRE can overdrive the pullup resistor while keeping PRE above its V_IH level.

Figure 2-1 SN74HC74 Partial Schematic for High Power-Up Output at Q

An alternative to waiting for V_CC to ramp is to add an RC circuit and Schmitt Trigger (Figure 2-2) buffer to delay the clock pulse. Design the RC for an appropriate time constant, which will depend on the signal frequency and desired CLK delay. The CLK signal behind the Schmitt Trigger will rise slowly, and the Schmitt Trigger will convert the slower edge to a fast edge. The resulting CLK signal coming out of the Schmitt Trigger will be delayed by a small amount. A weak pulldown on the output of the Schmitt Trigger may be necessary to avoid floating the CLK input. The pulldown resistor is not necessary if the device has Bus Hold.

Figure 2-2 Schmitt-Trigger Clock Delay Circuit

Another method for ensuring outputs is to wait until V_CC has ramped to an appropriate level before a clock edge occurs. If the application requires that CLK rise with V_CC, the user should wait one extra clock cycle to ensure valid outputs. For example, this means waiting for 9 clock pulses for the CD74HC4094 instead of the 8 mentioned earlier.