产品详情

Number of channels 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 35 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 40000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 35 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 40000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 SSOP (DB) 20 56.16 mm² 7.2 x 7.8
  • Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
  • 3-State Bus-Driving Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
  • P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)

  • Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
  • 3-State Bus-Driving Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
  • P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

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类型 标题 下载最新的英语版本 日期
* 数据表 Octal D-Type Transparent Latches And Edge-Triggered Flip-Flops 数据表 (Rev. B) 2002年 8月 23日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Designing with the SN54/74LS123 (Rev. A) 1997年 3月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日

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用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
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仿真模型

SN74LS374 IBIS Model (Rev. A)

SDLM010A.ZIP (6 KB) - IBIS Model
封装 引脚 下载
PDIP (N) 20 查看选项
SOIC (DW) 20 查看选项
SOP (NS) 20 查看选项
SSOP (DB) 20 查看选项

订购和质量

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  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 制造厂地点
  • 封装厂地点

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