SCEA117 July   2022 SN74HCS164 , SN74HCS164-Q1 , SN74HCS165 , SN74HCS165-Q1 , SN74HCS595 , SN74HCS595-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Types of Shift Registers
    2. 1.2 Default State of a Shift Register
    3. 1.3 164 Function Shift Registers
    4. 1.4 165 Function Shift Registers
    5. 1.5 595 Function Shift Registers
    6. 1.6 Daisy-Chain Two Shift Registers
  4. 2Design Challenges
    1. 2.1 Controller Loading Limits
    2. 2.2 Operating over Large Distances
    3. 2.3 Data Loss Due to Signal Timing
    4. 2.4 Data Rate Limitations
    5. 2.5 Software Overview
  5. 3Example Design - Daisy Chain 72 Shift Registers
    1. 3.1 System Overview
    2. 3.2 System Design
    3. 3.3 Software Examples
  6. 4References

1.2 Default State of a Shift Register

Shift registers, like many sequential logic devices, contain flip-flops which rely on the previous output state to determine the current output state. For example, see Table 1-1 for the common D-type Flip-Flop logical function table. The output when the clock is not being pulsed is purely dependent on the previous state, Q0.

Table 1-1 Typical D-type Flip-Flop Function Table
D CLK Q
L ↑ L
H ↑ H
X L, H, or ↓ Q0

Because of this dependency on the previous state, the values stored in a shift register are unknown at startup, and remain unknown until data is loaded into the registers. This can be problematic for some systems that depend on the outputs of the shift registers to be in a certain state at startup.

There are three ways around this. First, many shift registers include a direct clear pin to force all internal registers to a logic LOW. This allows a system designer to have a power-on-reset (POR) signal clear the registers immediately when power is applied.

The second, and most common, method is to load in data to overwrite the unknown values. It is common practice to have an initialization routine for shift registers that pushes initial values into all registers to prevent undesired behavior.

Finally, some devices provide the ability to put the outputs into a high-impedance state, which allows pull-up or pull-down resistors to set something of a default value at the outputs. Alternatively, 3-state buffers can be added to any shift register’s outputs to provide a high-impedance state. This should not be confused with changing the internal register values, however, as this method will only set the output values as long as they are in the high-impedance state. The internal registers are still unknown and must be overwritten before beginning operation.

Disabling the outputs with a POR signal combined with writing in known values can create a very effective initialization routine for a system with many shift registers. The POR just needs to last long enough for data to be written into the registers at system startup.

For details on creating a POR signal, please see this video: Generate a Reset Signal at System Power On