SCEA117 July   2022 SN74HCS164 , SN74HCS164-Q1 , SN74HCS165 , SN74HCS165-Q1 , SN74HCS595 , SN74HCS595-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Types of Shift Registers
    2. 1.2 Default State of a Shift Register
    3. 1.3 164 Function Shift Registers
    4. 1.4 165 Function Shift Registers
    5. 1.5 595 Function Shift Registers
    6. 1.6 Daisy-Chain Two Shift Registers
  4. 2Design Challenges
    1. 2.1 Controller Loading Limits
    2. 2.2 Operating over Large Distances
    3. 2.3 Data Loss Due to Signal Timing
    4. 2.4 Data Rate Limitations
    5. 2.5 Software Overview
  5. 3Example Design - Daisy Chain 72 Shift Registers
    1. 3.1 System Overview
    2. 3.2 System Design
    3. 3.3 Software Examples
  6. 4References

1.3 164 Function Shift Registers

The 164 function is an 8-bit parallel-out shift register. The serial data inputs are logically ANDed together to provide an easy method for disabling the register. If either A or B is in the LOW state, then the data input to the shift register is LOW, and each rising-edge clock input will load a LOW, irrespective of the state of the opposite input. To permanently enable the serial data input, either A or B can be tied directly to VCC, and the opposite input can be used as the serial data input.

Figure 1-1 Visual Representation of the Effect for Clock Input of 164 Function Shift Registers

When a rising edge is detected at the CLK input, the eight registers are loaded with the data value indicated by the arrows in Figure 1-1. To be clear, the result of A AND B is loaded into QA, while the value that was in QA is loaded into QB, the value that was in QB is loaded into QC, and so on. The last value, which was in QH, is shifted out, or, in other words, it is overwritten.

The 164 function comes with a dedicated asynchronous active-low clear pin (CLR) which allows forcing the internal register (and thus the output) values to zero. If this pin is held low during startup, the outputs will remain low as soon as the device is within the operating voltage range.

For normal functionality, eight bits of data are loaded into the serial data input one at a time with eight clock pulses. With each rising edge at the clock input, the outputs will change immediately to match the values inside the serial registers.

The output QH comes directly from the last internal shift register, which allows it to be used for daisy-chaining devices together.