SCEA117 July   2022 SN74HCS164 , SN74HCS164-Q1 , SN74HCS165 , SN74HCS165-Q1 , SN74HCS595 , SN74HCS595-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Types of Shift Registers
    2. 1.2 Default State of a Shift Register
    3. 1.3 164 Function Shift Registers
    4. 1.4 165 Function Shift Registers
    5. 1.5 595 Function Shift Registers
    6. 1.6 Daisy-Chain Two Shift Registers
  4. 2Design Challenges
    1. 2.1 Controller Loading Limits
    2. 2.2 Operating over Large Distances
    3. 2.3 Data Loss Due to Signal Timing
    4. 2.4 Data Rate Limitations
    5. 2.5 Software Overview
  5. 3Example Design - Daisy Chain 72 Shift Registers
    1. 3.1 System Overview
    2. 3.2 System Design
    3. 3.3 Software Examples
  6. 4References

2.1 Controller Loading Limits

Most CMOS logic circuits are designed to operate with relatively light loads. For example, the SN74LVC1G08, which has very strong output drivers, is designed to operate with a capacitive load of 50 pF or less (SN74LVC1G08, section 6.8). The SN74AUP1G08 has weaker output drivers and is specified for a load of 30 pF or less (SN74AUP1G08, section 6.9). For another example, the MSP430FR2311 has the output timing specified only up to 20 pF (MSP430FR2311, Table 5-11).

The output loading can usually be found in the data sheet timing specifications as a test condition. Most modern CMOS-based controllers will have relatively weak outputs, so it’s a good idea to avoid loading them too heavily. It is recommended to avoid exceeding the tested load values provided in the data sheet. This limit can be bypassed, however, by adding a buffer to redrive the signal.

Figure 2-1 Example of Signal Fanout Using Only Logic Buffers

Discrete buffers can be used as many times as necessary to redrive the signal. Creating duplicate signals from a single input is known as fanout and can be accomplished using normal discrete logic buffers such as the SN74HCS244. See Figure 2-1 for an example of redriving a single weak output to multiple 50 pF loads. Each buffer will add some delay to the signal, so be sure to follow the guidelines in Section 2.3 to avoid issues.