ZHCSDF1 February   2015 UCD90240

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Nonvolatile Memory Characteristics
    7. 6.7 I2C/PMBUS Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Device Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  TI Fusion GUI
      2. 7.3.2  PMBUS Interface
      3. 7.3.3  Rail Setup
      4. 7.3.4  Rail Monitoring Configuration
      5. 7.3.5  GPI Configuration
      6. 7.3.6  Rail Sequence Configuration
      7. 7.3.7  Fault Responses Configuration
      8. 7.3.8  GPO Configuration
        1. 7.3.8.1 Command Controlled GPO
        2. 7.3.8.2 Logic GPO
      9. 7.3.9  Margining Configuration
      10. 7.3.10 Pin Selected Rail States Configuration
      11. 7.3.11 Watchdog Timer
      12. 7.3.12 System Reset Function
      13. 7.3.13 Cascading Multiple Devices
      14. 7.3.14 Voltage Monitoring
      15. 7.3.15 Status Monitoring
      16. 7.3.16 Data and Error Logging to EEPROM Memory
      17. 7.3.17 Black Box First Fault Logging
      18. 7.3.18 PMBUS Address Selection
      19. 7.3.19 ADC Reference
      20. 7.3.20 Device Reset
      21. 7.3.21 Brownout
      22. 7.3.22 Device Configuration and Programming
      23. 7.3.23 Internal Fault Management
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Diagram
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The UCD90240 can be used to sequence, monitor and margin up to 24 voltage rails. With the cascading feature, up to four UCD90240 devices can manage up to 96 rails and take synchronized fault responses. Typical applications include automatic test equipment, telecommunication and networking equipment, servers and storage systems, and so forth. Device configuration can be performed in Fusion GUI. No coding skill is required.

8.2 Typical Application

Figure 32 shows a simplified system diagram. Only three rails are shown for illustration purpose. Each UCD90240 device can manage up to 24 rails.

8.2.1 Application Diagram

UCD90240 application_SLVSCW0.gifFigure 32. Simplified System Diagram

8.2.2 Design Requirements

  1. UCD90240 requires decoupling capacitors on V33D, V33A, BPCAP, and (if applicable) VREFA+ pins. The capacitance values for V33A, BPCAP and VREFA+ are specified in the Electrical Characteristics section. The following design can be used as a reference:
    • Three 1-μF X7R ceramic capacitors in parallel with two 0.1-μF X7R ceramic capacitors for BPCAP decoupling
    • Two 1-μF X7R ceramic capacitors in parallel with four 0.1-μF X7R ceramic capacitors and two 0.01-μF X7R ceramic capacitors for V33D decoupling
    • One 1-μF X7R ceramic capacitor in parallel with one 0.1-μF X7R ceramic capacitor and one 0.01-μF X7R ceramic capacitor for V33A decoupling. A 1-Ω resistor can placed between V33D and V33A to decouple the noise on V33D from V33A.
    • One 1-μF X7R ceramic capacitor in parallel with one 0.01-μF X7R ceramic capacitor for VREFA+ decoupling (if used)

      • Decoupling capacitors should be placed as close to the device as possible.

  2. If an application does not use the RESET signal, the RESET pin must be tied to V33D, either by direct connection to the nearest V33D pin (Pin F10), or by a RC circuit as shown in Figure 33. The RC circuit in Figure 33 can be also used to delay reset at power up.

    3. If an application uses the RESETexternal pin, the trace of the RESET signal must be kept as short as possible. Be sure to place any components connected to the RESET signal as close to the UCD90240 as possible.

  3. It is recommended to maintain at least 200-Ω resistance between a low-impedance analog input and a MON pin. For example, when monitoring a rail voltage without resistor divider, it is recommended to place a 200-Ω resistor at the MON pin, as shown in Figure 34.
UCD90240 reset_V33D_SLVSCW0.gifFigure 33. Example of RESET with RC Circuit
UCD90240 analog_input_SLVSCW0.gifFigure 34. Example of Analog Inputs

8.2.3 Detailed Design Procedure

Fusion GUI can be used to design the device configuration online or offline (with or without a UCD90240 device connected to the computer). In offline mode, Fusion GUI will prompt user to create or open a project file (.xml) at launch. In online mode, Fusion GUI will automatically detect the device on PMBus and extract the configuration data from the device. An USB Interface Adapter EVM (HPA172) from TI is required to connect Fusion GUI to PMBus.

The general design steps include (1) Rail setup, (2) Rail monitoring configuration, (3) GPI configuration, (4) Rail sequence configuration, (5) Fault response configuration, (6) GPO configuration, (7) Margining configuration, (8) Other configurations such as Pin Selected Rail States, Watchdog Timer, System Reset, Sync Clock, Fault Pins, and so on. Details of the steps are described in the Feature Description section, and are self-explanatory in Fusion GUI.

After configuration change(s), the user should click the Write to Hardware button to apply the changes. In online mode, the user can then click the Store RAM to Flash button to permanently store the new configuration into the data flash of the device.