ZHCSDF1 February   2015 UCD90240

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Nonvolatile Memory Characteristics
    7. 6.7 I2C/PMBUS Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Device Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  TI Fusion GUI
      2. 7.3.2  PMBUS Interface
      3. 7.3.3  Rail Setup
      4. 7.3.4  Rail Monitoring Configuration
      5. 7.3.5  GPI Configuration
      6. 7.3.6  Rail Sequence Configuration
      7. 7.3.7  Fault Responses Configuration
      8. 7.3.8  GPO Configuration
        1. 7.3.8.1 Command Controlled GPO
        2. 7.3.8.2 Logic GPO
      9. 7.3.9  Margining Configuration
      10. 7.3.10 Pin Selected Rail States Configuration
      11. 7.3.11 Watchdog Timer
      12. 7.3.12 System Reset Function
      13. 7.3.13 Cascading Multiple Devices
      14. 7.3.14 Voltage Monitoring
      15. 7.3.15 Status Monitoring
      16. 7.3.16 Data and Error Logging to EEPROM Memory
      17. 7.3.17 Black Box First Fault Logging
      18. 7.3.18 PMBUS Address Selection
      19. 7.3.19 ADC Reference
      20. 7.3.20 Device Reset
      21. 7.3.21 Brownout
      22. 7.3.22 Device Configuration and Programming
      23. 7.3.23 Internal Fault Management
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Diagram
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage applied at V33D to DVSS 0 4 V
Voltage applied at V33A to AVSS 0 4 V
Input voltage on all I/O pins except PMBUS_CNTRL, PMBALERT#, MARGIN19 and MARGIN20, regardless of whether the device is powered(2)(3) –0.3 5.5 V
Input voltage on PMBUS_CNTRL, PMBALERT#, MARGIN19 and MARGIN20 –0.3 V33D+0.3 V
Maximum current per output pin – 25 mA
Maximum junction temperature – 150 °C
Unpowered storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Applies to static and dynamic signals including overshoot.
(3) All I/O pins except PMBUS_CNTRL, PMBALERT#, MARGIN19 and MARGIN20 are tolerant to 5-V digital inputs without creating reliability issues, as long as the supply voltage, V33D, is present. There are limitations to how long a 5-V input can be present on any given I/O pin if V33D is not present. Not meeting these conditions will affect reliability of the device and affect the I/O pin characteristics specifications.
  1. If the voltage applied to an I/O pin is in the high voltage range (5V ± 10%) while V33D is not present, such condition should be allowed for a maximum of 10,000 hours at 27°C or 5,000 hours at 85°C, over the lifetime of the device.
  2. If the voltage applied to an I/O pin is in the normal voltage range (3.3V ± 10%) while V33D is not present or if the voltage applied is in the high voltage range (5V ± 10%) while V33D is present, there are no constraints on the lifetime of the device.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V33D supply voltage 3.15 3.3 3.63 V
V33A supply voltage(1) 2.97 3.3 3.63 V
TA Ambient operating temperature range –40 – +85 °C
TC Case operating temperature range –40 – +90 °C
TJ Junction operating temperature range –40 – +93 °C
(1) V33A and V33D should connect to the same supply. Otherwise, V33A must be powered before V33D if sourced from different supplies. There is no restriction on order for powering off.

6.4 Thermal Information

THERMAL METRIC(1) UCD90240 UNIT
BGA
157 PINS
RθJA Junction-to-ambient thermal resistance 41.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.8
RθJB Junction-to-board thermal resistance 18.9
ψJT Junction-to-top characterization parameter 0.3
ψJB Junction-to-board characterization parameter 20.3
RθJC(bot) Junction-to-case (bottom) thermal resistance
TJ Junction temperature formula TC + (P × ΨJT)
TPCB +(P × ΨJB)(2)
TA + (P × ΘJA)(3)
TB + (P × ΘJB)(4)(5)		 °C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) TPCB is the temperature of the board acquired by following the steps listed in the EAI/JESD 51-8 standard summarized in the Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953).
(3) Because ΘJA is highly variable and based on factors such as board design, chip/pad size, altitude, and external ambient temperature, it is recommended that equations containing ΨJT and ΨJB be used for best results.
(4) TB is temperature of the board.
(5) ΘJB is not a pure reflection of the internal resistance of the package because it includes the resistance of the testing board and environment. It is recommended that equations containing ΨJT and ΨJB be used for best results.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IV33 Supply current V33D = V33A = 3.3V – 31.4 54.9 mA
ON-CHIP LOW DROP-OUT (LDO) REGULATOR
CLDO External filter capacitor size for internal power supply(1) 2.5 – 4.0 µF
ESR Filter capacitor equivalent series resistance 10 – 100 mΩ
ESL Filter capacitor equivalent series inductance – – 0.5 nH
VLDO LDO output voltage 1.08 1.2 1.32 V
IINRUSH Inrush current 50 – 250 mA
ANALOG-TO-DIGITAL CONVERTER (ADC)(2)
V33A ADC supply voltage 2.97 3.3 3.63 V
AVSS ADC ground voltage – 0 – V
CV33A Voltage reference decoupling capacitance between V33A and AVSS – 1.0/0.01(4) –
VREFA+ Positive external voltage reference on VREFA+ pin 2.4 – 3 V
VREFA– Negative external voltage reference on VREFA– pin AVSS AVSS 0.3 V
CREF Voltage reference decoupling capacitance between VREFA+ and VREFA– (if using external reference) – 1.0/0.01(4) – µF
VADCIN Analog input range, internal reference(5) 0 – V33A V
Analog input range, external reference(6) VREFA– – VREFA+
IL ADC input leakage current – – 2.0 µA
RADC ADC equivalent input resistance 2.5 kΩ
CADC ADC equivalent input capacitance 10 pF
FCONV ADC conversion rate (on each ADC channel)(2) 1 MSPS
N ADC resolution 12 bits
ET Total unadjusted error, over full input range when using internal reference(3) ±10 ±30 LSB
Total unadjusted error, over full input range when using external reference(3) ±2.5 ±4.0
DIGITAL INPUTS AND OUTPUTS (GPIO, LOGIC GPO, EN, AND MARGIN PINS)
VIH I/O high-level input voltage(7) 0.65×V33D – 5.5V V
VIL I/O low-level input voltage 0 – 0.35×V33D V
VHYS I/O input hysteresis 0.2 – – V
VOH I/O high-level output voltage 2.4 – – V
VOL I/O low-level output voltage – – 0.4 V
IOH High-level source current, VOH = 2.4V(8) 4.0 – – mA
IOL Low-level sink current, VOL = 0.4V(8) 4.0 – – mA
RESET AND BROWNOUT
V33DSlew Minimum V33D slew rate between 2.8V and 3.2V 0.1 – – V/ms
VRESET Supply voltage at which device comes out of reset 2.85 3.00 3.15 V
VBOR Supply voltage at which device enters brownout 2.93 3.02 3.11 V
VSHDN Supply voltage at which device shuts down 2.70 2.78 2.87 V
tRESET Minimum low-pulse width needed at RESET pin – 250 – ns
tIRT Internal Reset Time(9) – 9 11.5 ms
(1) The capacitor should be connected as close as possible to pin D6.
(2) Total of two ADC channels run independently during normal operation.
(3) Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes offset error, gain error and INL at any given ADC code.
(4) Two capacitors in parallel
(5) Internal reference is connected directly between V33A and AVSS.
(6) External reference noise level must be under 12bit (–74 dB) of Full Scale input, over input bandwidth, measured at VREFA+ – VREFA–.
(7) PMBUS_CNTRL, PMBALERT#, MARGIN19 and MARGIN20 pins have V33D+0.3V as maximum input voltage rating.
(8) IO specifications reflect the maximum current where the corresponding output voltage meets the VOH/VOL thresholds.
(9) If power-loss or brown-out event occurs during an EEPROM program or erase operation, and EEPROM needs to be repaired (which is a rare case), the Internal Reset Time may be longer.

6.6 Nonvolatile Memory Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
CONFIGURATION FLASH MEMORY
PECYC Number of program/erase cycles before failure 100 000 – – Cycles
TRET Data retention, -40°C to +85°C 20 – – Years
FAULT AND EVENT LOGGING EEPROM
EPECYC Number of mass program/erase cycles of a single word before failure 500 000 – – Cycles
ETRET Data retention, -40°C to +85°C 20 – – Years

6.7 I2C/PMBUS Timing Requirements

PARAMETER MIN TYP MAX UNIT
I1 t(HD:STA) Start condition hold time 450 – – ns
I2 t(LOW) Clock Low period(1) 450 – – ns
I3 tr Clock/Data rise time(2) – – See (2) ns
I4 t(HD:DAT) Data hold time – 25 – ns
I5 tf Clock/Data fall time(3) – 112.5 125 ns
I6 t(HIGH) Clock High time 300 – – ns
I7 t(SU:DAT) Data setup time 225 – – ns
I8 t(SU:STA) Start condition setup time (Repeated start only) 450 – – ns
I9 t(SU:STO) Stop condition setup time 300 – – ns
I10 t(DV) Data Valid – 25 – ns
(1) PMBus host must support clock stretching per PMBus Power System Management Protocol Specification Part I General Requirements, Transport And Electrical Interface, Revision 1.2, Section 5.2.6.
(2) Because I2CSCL and I2CSDA operate as open-drain-type signals, which the controller can only actively drive Low, the time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pullup resistor values.
(3) Specified at a nominal 50 pF load.
UCD90240 LMI_I2C_timing_SLVSCW0.gif