ZHCSDF1 February   2015 UCD90240

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Nonvolatile Memory Characteristics
    7. 6.7 I2C/PMBUS Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Device Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  TI Fusion GUI
      2. 7.3.2  PMBUS Interface
      3. 7.3.3  Rail Setup
      4. 7.3.4  Rail Monitoring Configuration
      5. 7.3.5  GPI Configuration
      6. 7.3.6  Rail Sequence Configuration
      7. 7.3.7  Fault Responses Configuration
      8. 7.3.8  GPO Configuration
        1. 7.3.8.1 Command Controlled GPO
        2. 7.3.8.2 Logic GPO
      9. 7.3.9  Margining Configuration
      10. 7.3.10 Pin Selected Rail States Configuration
      11. 7.3.11 Watchdog Timer
      12. 7.3.12 System Reset Function
      13. 7.3.13 Cascading Multiple Devices
      14. 7.3.14 Voltage Monitoring
      15. 7.3.15 Status Monitoring
      16. 7.3.16 Data and Error Logging to EEPROM Memory
      17. 7.3.17 Black Box First Fault Logging
      18. 7.3.18 PMBUS Address Selection
      19. 7.3.19 ADC Reference
      20. 7.3.20 Device Reset
      21. 7.3.21 Brownout
      22. 7.3.22 Device Configuration and Programming
      23. 7.3.23 Internal Fault Management
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Diagram
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

  1. Decoupling capacitors should be placed as close to the device as possible.
  2. BPCAP decoupling capacitors should be connected as close as possible to pin D6.
  3. MARGIN pins output fast-edge PWM signals. These signals should be routed away from sensitive analog signals. It is a good practice to place R4 and C1 in Figure 16 as close as possible to the MARGIN pin, minimizing the propagation distance of the fast-edge PWM signals on the PCB. R3 can be placed near the power supply feedback node to isolate the feedback node from noise sources on the PCB. If R4 and C1 cannot be located close to the MARGIN pin, add a 20-Ω to 33-Ω series termination resistor located near the MARGIN pin.

10.2 Layout Example

UCD90240 is in a 157-pin BGA package. If UCD90240 is mounted on the top layer, decoupling capacitors can be placed on the bottom layer to make room for top-layer trace routing. The layout example below adopts such a strategy. Figure 35 shows bottom-layer component placement from top-view. In addition to Figure 35, note that:

  1. A uniform ground plane should be used to connect DVSS, AVSS, and VREFA– pins.
  2. All four BPCAP pins should be connected to a common internal-layer copper area.
  3. AVSS and VREFA– pins can be connected to a common internal-layer copper area.
UCD90240 Layout2_SLVSCW0.gifFigure 35. Bottom-layer Component Placement
(Top view, UCD90240 is Mounted on Top Layer)