SLUSA16D Data sheet | 德州仪器 TI.com.cn

SLUSA16D March 2010 – November 2016 UCC28950

PRODUCTION DATA.

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PW|24
- MPDS363A

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Input supply voltage, V_DD ⁽³⁾	–0.4	20	V
OUTA, OUTB, OUTC, OUTD, OUTE, OUTF	–0.4	VDD + 0.4	V
Input voltage on DELAB, DELCD, DELEF, SS/EN, DCM, TMIN, RT, SYNC, RSUM, EA+, EA-, COMP, CS, ADEL, ADELEF	–0.4	VREF + 0.4	V
Output voltage on VREF	–0.4	5.6	V
Continuous total power dissipation	See Dissipation Ratings
Operating virtual junction temperature, T_J	–40	+150	°C
Operating ambient temperature, T_A	–40	+125	°C
Lead temperature (soldering, 10 sec.)		+300	°C
Storage temperature, T_stg	–65	+150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.

(3) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Supply voltage range, V_DD	8	12	17	V
Operating junction temperature range	–40		125	°C
Converter switching frequency setting range, F_SW(nom)	50		1000	kHz
Programmable delay range between OUTA, OUTB and OUTC, OUTD set by resistors DELAB and DELCD and parameter K_A⁽¹⁾	30		1000	ns
Programmable delay range between OUTA, OUTF and OUTB, OUTE set by resistor DELEF, and parameter K_EF⁽¹⁾	30		1400	ns
Programmable DCM range as percentage of voltage at CS⁽¹⁾	5%		30%
Programmable T_MIN range	100		800	ns

(1) Verified during characterization only.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC28950	UNIT
		PW (TSSOP)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	93.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	24.2	°C/W
R_θJB	Junction-to-board thermal resistance	47.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.7	°C/W
ψ_JB	Junction-to-board characterization parameter	47.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

V_DD = 12 V, T_A = T_J = –40°C to +125°C, C_VDD = 1 µF, C_REF = 1 µF, R_AB = 22.6 kΩ, R_CD = 22.6 kΩ , R_EF = 13.3 kΩ, R_SUM = 124 kΩ, R_TMIN = 88.7 kΩ, R_T = 59 kΩ connected between RT pin and 5-V voltage supply to set F_SW = 100 kHz (F_OSC = 200 kHz) (unless otherwise noted). All component designations are from Figure 48.

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO_RTH	Start threshold		6.75	7.3	7.9	V
UVLO_FTH	Minimum operating voltage after start		6.15	6.7	7.2	V
UVLO_HYST	Hysteresis		0.53	0.6	0.75	V
SUPPLY CURRENTS
I_DD(off)	Startup current	V_DD is 5.2 V		150	270	µA
I_DD	Operating supply current			5	10	mA
VREF OUTPUT VOLTAGE
V_REF	VREF total output range	0 ≤ IR ≤ 20 mA; V_DD = from 8 V to 17 V	4.925	5	5.075	V
ISCC	Short circuit current	VREF = 0 V	–53		–23	mA
SWITCHING FREQUENCY (½ OF INTERNAL OSCILLATOR FREQUENCY F_OSC)
F_SW(nom)	Total range		92	100	108	kHz
D_MAX	Maximum duty cycle			95%	97%
SYNCHRONIZATION
PH_SYNC	Total range	R_T = 59 kΩ between RT and GND; Input pulses 200 kHz, D = 0.5 at SYNC	85	90	95	°PH
F_SYNC	Total range	R_T = 59 kΩ between RT and 5 V; –40 °C ≤ T_J ≤ +125°C	180	200	220	kHz
T_PW	Pulse width		2.2	2.5	2.8	µs
ERROR AMPLIFIER
V_ICM	Common mode input voltage range	V_ICM range ensures parameters, the functionality ensured for 3.6 V < V_ICM < VREF + 0.4 V, and –0.4 V < V_ICM < 0.5 V	0.5		3.6	V
V_IO	Offset voltage		– 7		7	mV
I_BIAS	Input bias current		–1		1	µA
EA_HIGH	High-level output voltage	(EA+) – (EA–) = 500 mV, I_EAOUT = –0.5 mA	3.9	4.25		V
EA_LOW	Low-level output voltage	(EA+) – (EA–) = –500 mV, I_EAOUT= 0.5 mA		0.25	0.35	V
I_SOURCE	Error amplifier source current		–8	–3.75	–0.5	mA
I_SINK	Error amplifier sink current		2.7	4.6	5.75	mA
I_VOL	Open-loop dc gain			100		dB
GBW	Unity gain bandwidth⁽¹⁾			3		MHz
CYCLE-BY-CYCLE CURRENT LIMIT
V_{CS_LIM}	CS pin cycle-by-cycle threshold		1.94	2	2.06	V
INTERNAL HICCUP MODE SETTINGS
I_DS	Discharge current to set cycle-by-cycle current limit duration	CS = 2.5 V, VSS = 4 V	15	20	25	µA
V_HCC	Hiccup OFF Time threshold		3.2	3.6	4.2	V
I_HCC	Discharge current to set Hiccup Mode OFF Time		1.90	2.55	3.2	µA
SOFT START/ENABLE
I_SS	Charge current	V_SS = 0 V	20	25	30	µA
V_{SS_STD}	Shutdown/restart/reset threshold		0.25	0.50	0.70	V
V_{SS_PU}	Pull up threshold		3.3	3.7	4.3	V
V_{SS_CL}	Clamp voltage		4.20	4.65	4.95	V
LIGHT-LOAD EFFICIENCY CIRCUIT
V_DCM	DCM threshold, T = 25°C	V_DCM = 0.4 V, Sweep CS confirm there are OUTE and OUTF pulses	0.37	0.39	0.41	V
	DCM threshold, T = 0°C to +85°C ⁽⁷⁾	V_DCM = 0.4 V, Sweep CS, confirm there are OUTE and OUTF pulses	0.364	0.390	0.416	V
	DCM threshold, T= –40°C to +125°C ⁽⁷⁾	V_DCM = 0.4 V, Sweep CS, confirm there are OUTE and OUTF pulses	0.35	0.39	0.43	V
I_{DCM_SRC}	DCM Sourcing Current	CS < DCM threshold	14	20	26	µA
OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
I_SINK/SRC	Sink/Source peak current⁽⁷⁾			0.2		A
R_SRC	Output source resistance	I_OUT = 20 mA	10	20	35	Ω
R_SINK	Output sink resistance	I_OUT = 20 mA	5	10	30	Ω
THERMAL SHUTDOWN
	Rising threshold⁽⁷⁾			160		°C
	Falling threshold⁽⁷⁾			140		°C
	Hysteresis			20		°C

(1) Typical values for T_A = 25°C

(2) See Figure 28 for timing diagram and T_ABSET1, T_ABSET2, T_CDSET1, T_CDSET2 definitions.

(3) See Figure 31 for timing diagram and T_AFSET1, T_AFSET2, T_BESET1, T_BESET2 definitions.

(4) Pair of outputs OUTC, OUTE and OUTD, OUTF always going high simultaneously.

(5) Outputs A or B are never allowed to go high if both outputs OUTE and OUTF are high.

(6) All delay settings are measured relative to 50% of pulse amplitude.

(7) Verified during characterization only.

6.6 Timing Requirements

		MIN	NOM	MAX	UNIT
CYCLE-BY-CYCLE CURRENT LIMIT
T_CS	Propagation delay from CS to OUTC and OUTD outputs Input pulse between CS and GND from zero to 2.5 V		100		ns
PROGRAMMABLE DELAY TIME SET ACCURACY AND RANGE⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾⁽⁶⁾
T_ABSET1	Short delay time set accuracy between OUTA and OUTB CS = ADEL = ADELEF = 1.8 V	32	45	56	ns
T_ABSET2	Long delay time set accuracy between OUTA and OUTB CS = ADEL = ADELEF = 0.2 V	216	270	325	ns
T_CDSET1	Short delay time set accuracy between OUTC and OUTD CS = ADEL = ADELEF = 1.8 V	32	45	56	ns
T_CDSET2	Long delay time set accuracy between OUTC and OUTD CS = ADEL = ADELEF = 0.2 V	216	270	325	ns
T_AFSET1	Short delay time set accuracy between falling OUTA, OUTF CS = ADEL = ADELEF = 0.2 V	22	35	48	ns
T_AFSET2	Long delay time set accuracy between falling OUTA, OUTF CS = ADEL = ADELEF = 1.8 V	190	240	290	ns
T_BESET1	Short delay time set accuracy between falling OUTB, OUTE CS = ADEL = ADELEF = 0.2 V	22	35	48	ns
T_BESET2	Long delay time set accuracy between falling OUTB, OUTE CS = ADEL = ADELEF = 1.8 V	190	240	290	ns
ΔT_ADBC	Pulse matching between OUTA rise, OUTD fall and OUTB rise, OUTC fall CS = ADEL = ADELEF = 1.8 V, COMP = 2 V	–50	0	50	ns
ΔT_ABBA	Half cycle matching between OUTA rise, OUTB rise and OUTB rise, OUTA rise CS = ADEL = ADELEF = 1.8 V, COMP = 2 V	–50	0	50	ns
ΔT_EEFF	Pulse matching between OUTE fall, OUTE rise and OUTF fall, OUTF rise CS = ADEL = ADELEF = 0.2 V, COMP = 2 V	–60	0	60	ns
ΔT_EFFE	Pulse matching between OUTE fall, OUTF rise and OUTF fall, OUTE rise CS = ADEL = ADELEF = 0.2 V, COMP = 2 V	–60	0	60	ns
LIGHT-LOAD EFFICIENCY CIRCUIT
T_MIN	Total range, R_TMIN = 88.7 kΩ	425	525	625	ns
OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
T_R	Rise time, C_LOAD = 100 pF		9	25	ns
T_F	Fall time, C_LOAD = 100 pF		7	25	ns

6.7 Dissipation Ratings

over operating free-air temperature range (unless otherwise noted)

PACKAGE	DERATING FACTOR	POWER RATING
PACKAGE	ABOVE T_A = 25°C	T_A < 25°C	T_A = 70°C	T_A = 85°C
PW	10.7 mW/°C	1.07 W	0.59 W	0.429 W

No output delay shown, COMP-to-RAMP offset not included.

There is no pulse on OUTE during burst mode at startup. Two falling edge PWM pulses are required before enabling the synchronous rectifier outputs. Narrower pulse widths (less than 50% duty cycle) may be observed in the first OUTD pulse of a burst. The user must design the bootstrap capacitor charging circuit of the gate driver device so that the first OUTC pulse is transmitted to the MOSFET gate in all cases. Transformer based gate driver circuits are not affected. This behavior is described in more detail in the application note, Gate Driver Design Considerations.

Figure 1. UCC28950 Startup Timing Diagram