14 |
ADEL |
I |
Dead-time programming for the primary switches over CS voltage range, TABSET and TCDSET. |
13 |
ADELEF |
I |
Delay-time programming between primary side and secondary side switches, TAFSET and TBESET. |
4 |
COMP |
I/O |
Error amplifier output and input to the PWM comparator. |
15 |
CS |
I |
Current sense for cycle-by-cycle over-current protection and adaptive delay functions. |
12 |
DCM |
I |
DCM threshold setting. |
6 |
DELAB |
I |
Dead-time delay programming between OUTA and OUTB. |
7 |
DELCD |
I |
Dead-time delay programming between OUTC and OUTD. |
8 |
DELEF |
I |
Delay-time programming between OUTA to OUTF, and OUTB to OUTE. |
2 |
EA+ |
I |
Error amplifier non-inverting input. |
3 |
EA– |
I |
Error amplifier inverting input. |
24 |
GND |
— |
Ground. All signals are referenced to this node. |
22 |
OUTA |
O |
0.2-A sink/source primary switching output. |
21 |
OUTB |
O |
0.2-A sink/source primary switching output. |
20 |
OUTC |
O |
0.2-A sink/source primary switching output. |
19 |
OUTD |
O |
0.2-A sink/source primary switching output. |
18 |
OUTE |
O |
0.2-A sink/source synchronous switching output. |
11 |
RSUM |
I |
Slope compensation programming. Voltage mode or peak current mode setting. |
10 |
RT |
I |
Oscillator frequency set. Master or slave mode setting. |
5 |
SS/EN |
I |
Soft-start programming, device enable and hiccup mode protection circuit. |
16 |
SYNC |
I/O |
Synchronization out from Master controller to input of slave controller. |
17 |
OUTF |
O |
0.2-A sink/source synchronous switching output. |
9 |
TMIN |
I |
Minimum duty cycle programming in burst mode. |
23 |
VDD |
I |
Bias supply input. |
1 |
VREF |
O |
5-V, ±1.5%, 20-mA reference voltage output. |