ZHCSGJ1 August   2017 UCC27712-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化原理图
      2.      典型传播延迟比较
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Under Voltage Lockout
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Level Shift
      6. 7.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 7.3.7 Parasitic Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum Input Pulse Operation
      2. 7.4.2 Output Interlock and Dead Time
      3. 7.4.3 Operation Under 100% Duty Cycle Condition
      4. 7.4.4 Operation Under Negative HS Voltage Condition
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 8.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 8.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 8.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 8.2.2.6 Selecting Bootstrap Diode
        7. 8.2.2.7 Estimate the UCC27712-Q1 Power Losses (PUCC27712-Q1)
        8. 8.2.2.8 Estimating Junction Temperature
        9. 8.2.2.9 Operation With IGBT's
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 相关链接
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Selecting Gate Resistor RON/ROFF

Resistor RON and ROFF are sized to achieve the following:

  • Limit ringing caused by parasitic inductances and capacitances.
  • Limit ringing caused by high voltage/current switching dV/dt, dI/dt, and body diode reverse recovery.
  • Fine-tune gate drive strength to optimize switching loss.
  • Reduce electromagnetic interference (EMI).

As mentioned in Output Stage, the UCC27712-Q1 has a pull up structure with a P-channel MOSFET providing a peak source current of 1.8A.

For this example 3.3-Ω resistors for RON and 2.2-Ω resistors for ROFF were selected to provide damping for ringing and ample gate drive current.

Equation 6. UCC27712-Q1 qu6_slusce9.gif

Therefore the peak source current can be predicted with:

Equation 7. UCC27712-Q1 qu7_slusce9.gif
Equation 8. UCC27712-Q1 qu8_slusce9.gif

where

  • RON: External turn-on resistance
  • RGFET_Int: Power transistor internal gate resistance, found in the power transistor datasheet.
  • IO+ = Peak source current. The maximum values between 1.8 A, the UCC27712-Q1 peak source current, and the calculated value based on the gate drive loop resistance.

In this example:

Equation 9. UCC27712-Q1 qu9_slusce9.gif
Equation 10. UCC27712-Q1 qu10_slusce9.gif

Therefore, the high-side and low side peak source current is 1.6 A. Similarly, the peak sink current can be calculated with:

Equation 11. UCC27712-Q1 qu11_slusce9.gif
Equation 12. UCC27712-Q1 qu12_slusce9.gif

where

  • ROFF: External turn-off resistance
  • VDGATE: The diode forward voltage drop which is in series with ROFF. The diode in this example is an MBRM130L.
  • IO- = Peak sink current. The maximum values between 2.8 A, the UCC27712-Q1 peak sink current, and the calculated value based on the gate drive loop resistance.

In this example:

Equation 13. UCC27712-Q1 qu13_slusce9.gif
Equation 14. UCC27712-Q1 qu14_slusce9.gif