ZHCSTB0E February   2010  – November 2023 UCC27321-Q1 , UCC27322-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 说明（续）
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Source and Sink Capabilities During Miller Plateau
      4. 8.3.4 VDD
      5. 8.3.5 Drive Current and Power Requirements
      6. 8.3.6 Enable
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-to-Output Configuration
        2. 9.2.2.2 Input Threshold Type
        3. 9.2.2.3 VDD Bias Supply Voltage
        4. 9.2.2.4 Peak Source and Sink Currents
        5. 9.2.2.5 Enable and Disable Function
        6. 9.2.2.6 Propagation Delay
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1.     40
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
    4. 11.4 Power Dissipation
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics

VDD = 4.5 V to 15 V, TJ = TA = –40°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IDDStatic operating currentUCC27321-Q1IN = Low, ENBL = Low, VDD = 15 V150225µA
440650
IN = High, ENBL = Low, VDD = 15 V370550
370550
UCC27322-Q1IN = Low, ENBL = High, VDD = 15 V150225
450650
IN = High, ENBL = High, VDD = 15 V75125
6751000
INPUT (IN)
VIHLogic 1 input threshold1.62.22.5V
VILLogic 0 input threshold1.11.82.0V
Input current0 V ≤ VIN ≤ VDD–10010µA
OUTPUT (OUT)
Peak output current(1)VDD = 14 V9A
ROHOutput resistance high(2)IOUT = –10 mA0.61.5Ω
ROLOutput resistance low(2)IOUT = 10 mA0.41Ω
ENABLE (ENBL)
VEN_HEnable rising threshold voltageLow-to-high transitions1.52.22.7V
VEN_LEnable falling threshold voltageHigh-to-low transition1.11.652V
Hysteresis0.180.550.9V
R(ENBL)Enable impedanceVDD = 14 V, ENBL = Low75100145kΩ
tD3Propagation delay timeCLOAD = 10 nF (see Figure 7-2)6095ns
tD4Propagation delay timeCLOAD = 10 nF (see Figure 7-2)6095ns
(1) Parameter not tested in production
(2) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.