SLUS873C January   2009  – December 2016 UC1825A-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Leading Edge Blanking
      2. 8.3.2 UVLO, Soft-Start, and Fault Management
      3. 8.3.3 Active Low Outputs During UVLO
      4. 8.3.4 Control Methods
      5. 8.3.5 Synchronization
      6. 8.3.6 High Current Outputs
      7. 8.3.7 Open Loop Test Circuit
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Auxiliary Supply Voltage
        2. 9.2.2.2  Oscillator Frequency
        3. 9.2.2.3  Preliminary Considerations
        4. 9.2.2.4  Input Power
        5. 9.2.2.5  Primary Current
        6. 9.2.2.6  Sense Resistor R(s)
        7. 9.2.2.7  MOSFET DC Losses
        8. 9.2.2.8  Selection of Core Material
        9. 9.2.2.9  Main Transformer Design
        10. 9.2.2.10 Calculation of Transformer
        11. 9.2.2.11 Minimum Core Size
        12. 9.2.2.12 Core Loss Limited Conditions
        13. 9.2.2.13 Core Geometry Selection
        14. 9.2.2.14 Wire Size Selection
        15. 9.2.2.15 Calculate Secondary RMS Current
        16. 9.2.2.16 Transformer Assembly
        17. 9.2.2.17 Calculation of Winding Resistances and Losses
        18. 9.2.2.18 Transformer Power Losses
        19. 9.2.2.19 Output Section
          1. 9.2.2.19.1 Output Choke Calculations
          2. 9.2.2.19.2 Output Capacitor
          3. 9.2.2.19.3 Output Diodes
        20. 9.2.2.20 UC1825A-SP PWM Control Section
          1. 9.2.2.20.1 Current Limit and Shutdown
          2. 9.2.2.20.2 Ramp
          3. 9.2.2.20.3 Slope Compensation
        21. 9.2.2.21 Closing the Feedback Loop
          1. 9.2.2.21.1 Error Amplifier
          2. 9.2.2.21.2 Control to Output Gain
          3. 9.2.2.21.3 Error Amplifier Compensation
          4. 9.2.2.21.4 Dynamic Performance
          5. 9.2.2.21.5 Short Circuit
          6. 9.2.2.21.6 Circuit Power Losses
        22. 9.2.2.22 Summary
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Feedback Traces
      2. 11.1.2 Input/Output Capacitors
      3. 11.1.3 Compensation Components
      4. 11.1.4 Traces and Ground Planes
      5. 11.1.5 Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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10 Power Supply Recommendations

The UC1825A-SP is designed to operate from an input voltage supply range between 12 V and 20 V. This input supply should be well regulated. If the input supply is located more than few inches from the UC1825-SP converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. A tantalum capacitor with a value of 47 uf is a typical choice; however, this may vary depending upon the output power being delivered.

The UC1825A-SP controller can be used to convert power efficiently using any of several standard topologies such as push-pull, forward, half-bridge, or full bridge. Design tradeoffs of cost, size, and performance narrow the field to the one that is most appropriate. For a typical application, such as in Figure 16, push-pull converter topology is highlighted.