ZHCSF18E May   2016  – May 2019 TUSB1002

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, Power Supply
    6. 6.6  Electrical Characteristics
    7. 6.7  Power-Up Requirements
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Control Inputs
      2. 7.3.2 Linear Equalization
      3. 7.3.3 Adjustable VOD Linear Range and DC Gain
      4. 7.3.4 Receiver Detect Control
      5. 7.3.5 USB3.1 Dual Channel Operation (MODE = “F”)
      6. 7.3.6 USB3.1 Single Channel Operation (MODE = “1”)
      7. 7.3.7 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Disconnect Mode
    5. 7.5 U0 Mode
    6. 7.6 U1 Mode
    7. 7.7 U2/U3 Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical USB3.1 Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical SATA, PCIe and SATA Express Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.1 4-Level Control Inputs

The TUSB1002 has (MODE, CFG1, CFG2, CH1_EQ1, CH1_EQ2, CH2_EQ1, and CH2_EQ2) 4-level inputs pins that are used to control the equalization gain and the output voltage swing dynamic range. These 4-level inputs use a resistor divider to help set the 4 valid levels and provide a wider range of control settings. There is an internal 45 kΩ pull-up and a 95 kΩ pull-down. These resistors, together with the external resistor connection combine to achieve the desired voltage level.

Table 1. 4-Level Control Pin Settings

LEVEL SETTINGS
0 Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
R Tie 20 KΩ 5% to GND.
F Float (leave pin open)
1 Option 1: Tie 1 KΩ 5% to VCC.
Option 2: Tie directly to VCC.

NOTE

In order to conserve power, the TUSB1002 disables 4-level input’s internal pull-up/pull-down resistors after the state of 4-level pins have been sampled on rising edge of EN. A change of state for any four level input pin is not applied to TUSB1002 until after EN pin transitions from low to high.