ZHCSHH6B January   2018  – JANUARY 2019 TPSM846C24

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化电路原理图
      2.      效率与输出电流间的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 5 V)
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum Capacitance Requirements
      2. 7.3.2  Setting the Compensation Network
      3. 7.3.3  Transient Response
      4. 7.3.4  Setting the Output Voltage
      5. 7.3.5  Differential Remote Sense
      6. 7.3.6  Switching Frequency and Synchronization
        1. 7.3.6.1 Setting the Switching Frequency
        2. 7.3.6.2 Synchronization
          1. 7.3.6.2.1 Stand-Alone Device Synchronization
          2. 7.3.6.2.2 Paralleled Devices Synchronization
      7. 7.3.7  Prebiased Output Start-Up
      8. 7.3.8  Power-Good (PGOOD) Indicator
      9. 7.3.9  Linear Regulators BP3 and BP6
      10. 7.3.10 Parallel Application
      11. 7.3.11 Parallel Operation
      12. 7.3.12 Overtemperature Protection
      13. 7.3.13 Overcurrent Protection
      14. 7.3.14 Output Overvoltage and Undervoltage Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
        2. 8.1.2.2 Setting the Output Voltage
        3. 8.1.2.3 Input and Output Capacitance
        4. 8.1.2.4 Selecting the Compensation Components
        5. 8.1.2.5 Setting the Switching Frequency
        6. 8.1.2.6 Power Good (PGOOD)
        7. 8.1.2.7 ON/OFF Control (EN)
      3. 8.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Specifications
    4. 10.4 EMI
    5. 10.5 Mounting and Thermal Profile Recommendation
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息
    1. 12.1 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Guidelines

Layout is critical for good power-supply design. Figure 20 and Figure 21 show top-side and bottom-side PCB-layout configuration for recommended component placement. Additional power, ground and signal layers are present in any PCB design. A list of PCB layout considerations using these devices is listed as follows:

  • Place the input bypass capacitors as close as physically possible to the VIN and PGND pins. Additionally, a high-frequency bypass capacitor on the VIN pins can help reduce switching spikes. This capacitor can be placed on the bottom side of the PCB directly underneath the device to keep a minimum loop.
  • The BP6 bypass capacitor carries a large switching current for the gate driver. Bypassing the BP6 pin to BP6_RTN with a low-impedance path is very critical to the stable operation of the TPSM846C24 device. Place the BP6 high-frequency bypass capacitor as close as possible to the device pins 48 and 49.
  • The VINBP and BP3 pins also require good local bypassing. Place bypass capacitors as close as possible to the device pins and BP_RTN. Poor bypassing on the VINBP and BP3 pins can degrade the performance of the device.
  • Place signal components as close as possible to the pins to which they are connected. These components include the feedback resistors and the RT resistor. Keep these components away from fast switching voltage and current paths. Terminate these components to AGND with a minimum return loop.
  • Route the VS+ and VS– lines from the output capacitor bank at the load back to the device pins as a tightly coupled differential pair. These traces must be kept away from switching or noisy areas which can add differential-mode noise.
  • Use caution when routing of the SYNC, VSHARE and ISHARE traces for parallel configurations. The SYNC trace carries a rail-to-rail signal and must be routed away from sensitive analog signals, including the VSHARE, ISHARE, RT, and FB signals. The VSHARE and ISHARE traces must also be kept away from fast switching voltages or currents formed by the VIN, PH, and BP6 pins.