ZHCSRP2B February   2023  – December 2023 TPS7H3302-SEP , TPS7H3302-SP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN Control (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VTT Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 VTT Output Capacitor
        4. 8.2.2.4 VTTSNS Connection
        5. 8.2.2.5 Low VDD Applications
        6. 8.2.2.6 S3 and Pseudo-S5 Support
        7. 8.2.2.7 Tracking Startup and Shutdown
        8. 8.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
        9. 8.2.2.9 LDO Design Guidelines
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

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机械数据 (封装 | 引脚)
  • DAP|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.2.2.7 Tracking Startup and Shutdown

The TPS7H3302 supports tracking startup of VDDQ and shutdown when EN is tied directly to the system bus and not used to turn on or turn off the device. During tracking startup, VTT follows VTTREF once VDDQSNS voltage is greater than 0.75 V. VDDQSNS incorporates a resistor divider network and a time constant of about 445 µs. The rise time of the VTT output is then a function of the rise time of VDDQSNS. If the VDDQSNS rise time is larger than 445 µs. Typically PGOOD is asserted 4 ms after VTT is within ±20% of VTTREF. During tracking shutdown, VTT falls following VTTREF until VTTREF reaches 0.37 V (typically). Once VTTREF falls below 0.37 V, the internal discharge MOSFETs are turned on and quickly discharge both VTTREF and VTT to GND. PGOOD is deasserted once VTT is beyond the ±20% range of VTTREF. Figure 8-4 shows the typical timing diagram for an application that uses tracking startup and shutdown.

There are no sequencing requirements between VDD and VLDOIN. If VLDOIN is applied first followed by VDD there is no issue. VDD UVLO protection monitors VDD voltage. When VDD is lower than UVLO threshold both VTT and VTTREF regulators are powered off.

GUID-20230131-SS0I-ZS0Q-6PMS-RVHQJN9Q4JQM-low.svg Figure 8-4 Typical Timing Diagram of Tracking Startup and Shutdown