ZHCSI58C October   2009  – May 2018 TPS65720 , TPS65721

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     典型应用原理图
  4. 4 修订历史记录
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
    1.     Pin Functions—DSBGA (TPS65720)
    2.     Pin Functions—DSBGA (TPS657201, TPS657202)
    3.     Pin Functions—WQFN (TPS65721)
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Battery Charger and Power Path
      2. 8.3.2  Power-Path Management
      3. 8.3.3  Battery Charging
        1. 8.3.3.1 I-PRECHARGE
        2. 8.3.3.2 ITERM
        3. 8.3.3.3 Battery Detection and Recharge
        4. 8.3.3.4 Charge Termination On/Off
        5. 8.3.3.5 Timers
        6. 8.3.3.6 Dynamic Timer Function
        7. 8.3.3.7 Charger Fault
      4. 8.3.4  Thermal Regulation and Thermal Shutdown
      5. 8.3.5  Battery Pack Temperature Monitoring
      6. 8.3.6  DCDC1 Converter
      7. 8.3.7  Power Save Mode
        1. 8.3.7.1 Dynamic Voltage Positioning
        2. 8.3.7.2 Soft Start
        3. 8.3.7.3 100% Duty Cycle Low Dropout Operation
        4. 8.3.7.4 Undervoltage Lockout
      8. 8.3.8  Short-Circuit Protection
      9. 8.3.9  Thermal Shutdown
      10. 8.3.10 LDO1
        1. 8.3.10.1 Default Voltage Setting for LDOs and DCDC1
        2. 8.3.10.2 Internal Analog Multiplexer (BAT, TS, TS_OUT); TPS657201, TPS657202 Only
        3. 8.3.10.3 Internal Battery Voltage Comparator
        4. 8.3.10.4 GPIOs, LED Drivers
        5. 8.3.10.5 RESET Output
        6. 8.3.10.6 Threshold Input (TPS65721 Only)
          1. 8.3.10.6.1 ENABLE for DCDC1 and LDO1
          2. 8.3.10.6.2 PB_IN Input
          3. 8.3.10.6.3 HOLD_DCDC1 Input
          4. 8.3.10.6.4 HOLD_LDO1 Input
          5. 8.3.10.6.5 INT Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down
      2. 8.4.2 Sleep Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Power-On Reset Mode
      5. 8.4.5 Idle Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1  CHGSTATUS Register Address: 01h (read only)
      2. 8.6.2  CHGCONFIG0 Register Address: 02h (read/write)
      3. 8.6.3  CHGCONFIG1 Register Address: 03h (read/write)
      4. 8.6.4  CHGCONFIG2 Register Address: 04h (read/write)
      5. 8.6.5  CHGCONFIG3 Register Address: 05h (read/write)
      6. 8.6.6  CHGSTATE Register Address: 06h (read only)
      7. 8.6.7  DEFDCDC1 Register Address: 07h (read/write)
      8. 8.6.8  LDO_CTRL Register Address: 08h (read/write)
      9. 8.6.9  CONTROL0 Register Address: 09h (read/write)
      10. 8.6.10 CONTROL1 Register Address: 0Ah (read/write)
      11. 8.6.11 GPIO_SSC Register Address: 0Bh (read/write)
      12. 8.6.12 GPIODIR Register Address: 0Ch (read/write)
      13. 8.6.13 IRMASK0 Register Address: 0Dh (read/write)
      14. 8.6.14 IRMASK1 Register Address: 0Eh (read/write)
      15. 8.6.15 IRMASK2 Register Address: 0Fh (read/write)
      16. 8.6.16 IR0 Register Address: 10h (read only)
      17. 8.6.17 IR1 Register Address: 11h (read)
      18. 8.6.18 IR2 Register Address: 12h (read)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 DCDC1
          2. 9.2.2.1.2 LDO1
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
        3. 9.2.2.3 Charger/Power Path
          1. 9.2.2.3.1 Charger Stability
          2. 9.2.2.3.2 Setting the Charge Current
          3. 9.2.2.3.3 Dynamic Power Path Management (DPPM)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 接收文档更新通知
    5. 12.5 社区资源
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 说明

TPS6572x 器件是一种小型电源管理装置，专用于蓝牙耳机或其他便携式低功耗终端设备。该器件包含一个支持 USB 的锂离子充电器、一个高效的降压转换器和一个低压降线性稳压器，同时还具备其他支持功能。该器件由 I2C 接口来控制。可使用出厂时经过编程的非易失性内存来自定义多个设置。

为了在最大可能的负载电流范围内实现最大效率，2.25MHz 的降压转换器在轻负载时进入低功耗模式。对于低噪声 应用， 这些器件可通过与 I2C 兼容的接口强制进入固定频率 PWM 模式。

为了实现小解决方案尺寸，该器件允许使用小型电感器和电容器。TPS65720 可在直流/直流转换器上提供
高达 200mA 的输出电流，而 TPS657201、TPS657202 和 TPS65721 可提供高达 400mA 的输出电流。TPS6572x 还集成了一个 200mA 的 LDO。该 LDO 可在 1.8V 至 5.6V 输入电压范围内正常运行，这使得它可以由降压转换器的输出供电，也可以由系统电压直接供电。

TPS65720、TPS657201 和 TPS657202 采用焊球间距为 0.4mm 的小型 25 焊球 2mm × 2mm 晶圆芯片级封装 (DSBGA) 或者
间距为 0.4mm 的 4mm × 4mm WQFN 封装 (TPS65721)。

器件信息 (1)

器件型号 封装 封装尺寸（标称值）
TPS65720x DSBGA (25) 2.11mm × 2.11mm
TPS65721 WQFN (32) 4.00mm × 4.00mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

典型应用原理图

TPS65720 TPS657201 TPS657202 TPS65721 alt_slvs979.gif