ZHCSEO1C March   2012  – February 2016 TPS65177 , TPS65177A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 I2C Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up
        1. 7.3.1.1 TPS65177
        2. 7.3.1.2 TPS65177A
      2. 7.3.2 Power-Down
      3. 7.3.3 Thermal Shutdown
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Short-Circuit and Overload Protection
        1. 7.3.5.1 Boost Converter (V(AVDD)):
        2. 7.3.5.2 Buck 1 Converter (V(IO)):
        3. 7.3.5.3 Buck 2 Converter (V(CORE)):
        4. 7.3.5.4 Buck 3 Converter (V(HAVDD)):
        5. 7.3.5.5 Positive Charge-Pump Controller (V(GH)):
        6. 7.3.5.6 Negative Charge-Pump Controller (V(GL)):
    4. 7.4 Device Functional Modes
      1. 7.4.1 Boost Converter (V(AVDD))
        1. 7.4.1.1 Soft-Start
        2. 7.4.1.2 Compensation
        3. 7.4.1.3 Setting the Output Voltage V(AVDD)
        4. 7.4.1.4 High Voltage Stress Mode (HVS)
        5. 7.4.1.5 Programmable Current Limit
        6. 7.4.1.6 Design Procedure
        7. 7.4.1.7 Inductor Selection
        8. 7.4.1.8 Rectifier Diode Selection
          1. 7.4.1.8.1 Diode Type
          2. 7.4.1.8.2 Forward Voltage
          3. 7.4.1.8.3 Reverse Voltage
          4. 7.4.1.8.4 Thermal Characteristics
        9. 7.4.1.9 Output Capacitor Selection
      2. 7.4.2 Buck 1 Converter (V(IO))
        1. 7.4.2.1 Soft-Start
        2. 7.4.2.2 Setting the Output Voltage V(IO)
        3. 7.4.2.3 Design Procedure
        4. 7.4.2.4 Inductor Selection
        5. 7.4.2.5 Rectifier Diode Selection
          1. 7.4.2.5.1 Diode Type
          2. 7.4.2.5.2 Forward Voltage
          3. 7.4.2.5.3 Reverse Voltage
          4. 7.4.2.5.4 Forward Current
          5. 7.4.2.5.5 Thermal Characteristics
        6. 7.4.2.6 Output Capacitor Selection
      3. 7.4.3 BUCK 2 CONVERTER (V(CORE))
        1. 7.4.3.1 Soft-Start
        2. 7.4.3.2 Setting the Output Voltage V(CORE)
        3. 7.4.3.3 Design Procedure
        4. 7.4.3.4 Inductor Selection
        5. 7.4.3.5 Output Capacitor Selection
      4. 7.4.4 Buck 3 Converter (V(HAVDD))
        1. 7.4.4.1 Soft-Start
        2. 7.4.4.2 Setting the Output Voltage V(HAVDD)
        3. 7.4.4.3 High Voltage Stress Mode (HVS)
        4. 7.4.4.4 Design Procedure
        5. 7.4.4.5 Inductor Selection
        6. 7.4.4.6 Output Capacitor Selection
      5. 7.4.5 Positive Charge Pump Controller (V(GH)) with Temperature Compensation
        1. 7.4.5.1 Soft-Start
        2. 7.4.5.2 Setting the Output Voltage V(GH)
        3. 7.4.5.3 Design Procedure
        4. 7.4.5.4 Output Capacitor Selection
      6. 7.4.6 Negative Charge Pump Controller (V(GL))
        1. 7.4.6.1 Soft-Start
        2. 7.4.6.2 Setting the Output Voltage V(GL)
        3. 7.4.6.3 Design Procedure
        4. 7.4.6.4 Output Capacitor Selection
    5. 7.5 Gate Pulse Modulation (V(GHM))
    6. 7.6 Programming
      1. 7.6.1  I2C Serial Interface Description
      2. 7.6.2  Memory Description
      3. 7.6.3  Read / Write Description
      4. 7.6.4  Write Operation
        1. 7.6.4.1 Write Single Byte to the DAC Register (DR):
        2. 7.6.4.2 Write Multiple Bytes to the DAC Register (DR):
        3. 7.6.4.3 Write All DAC Register (DR) Data to EEPROM (EE):
      5. 7.6.5  READ OPERATION
        1. 7.6.5.1 Read single data from DAC register (DR):
        2. 7.6.5.2 Read Multiple Data from DAC Register (DR):
        3. 7.6.5.3 Read Single Data to EEPROM (EE):
        4. 7.6.5.4 Read Multiple Data to EEPROM (EE):
      6. 7.6.6  Write Single Data to DAC:
      7. 7.6.7  Write Multiple Data to DAC (Auto Increment Address):
      8. 7.6.8  Write all DAC Data to EEPROM:
      9. 7.6.9  Read Single Data From DAC / EEPROM:
      10. 7.6.10 Read Multiple Data fFom DAC / EEPROM (Auto Increment Address):
    7. 7.7 Register Map
      1. 7.7.1 Registers and DAC Settings
        1. 7.7.1.1  Channel Register (with factory value) - 00h (00h)
        2. 7.7.1.2  Boost Output Voltage V(AVDD) Register (with factory value) - 01h (0Fh)
        3. 7.7.1.3  Boost HVS Offset Voltage Register (with factory value) - 02h (05h)
        4. 7.7.1.4  Boost Current Limit Negative Offset Current Register (with factory value) - 03h (00h)
        5. 7.7.1.5  Boost Soft-start Time Register (with factory value) - 04h (00h)
        6. 7.7.1.6  Buck 1 Output Voltage V(IO) Register (with factory value) - 05h (03h):
        7. 7.7.1.7  Buck 2 Output Voltage V(CORE) Register (with factory value) - 06h (02h)
        8. 7.7.1.8  Buck 3 Output Voltage V(HAVDD) Register (with factory value) - 07h (1Bh)
        9. 7.7.1.9  Pos. Charge Pump Low Output Voltage V(GH_L) Register (with factory value) - 08h (08h):
        10. 7.7.1.10 Positive Charge Pump Low Output Voltage V(GH_L) to V(GH_H) Positive Offset Voltage V(GH_OFS) Register (with factory value) - 09h (04h):
        11. 7.7.1.11 Gate Pulse Modulation Limit Voltage Register (with factory value) - 0Ah (00h)
        12. 7.7.1.12 Negative Charge Pump Output Voltage V(GL) Register (with factory value) - 0Bh (04h)
        13. 7.7.1.13 Buck 3 HVS Offset Voltage Register (with factory value) - 0Ch (00h):
        14. 7.7.1.14 Memory Write Remain Time Register (with factory value) - FEh (0Fh):
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guideline
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 相关链接
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guideline

The PCB layout is a very important step in the power supply design. Following points should be considered.

  • Place red marked components first and as close as possible to the device, keep red lines short.
  • The bolder the line the wider the trace should be on the PCB because bold lines carry high currents.
  • The input capacitors for INBK1, INBK3 and INVL should be placed as close as possible to the IC.
  • For V(AVDD) the line SW, Diode, SWI as well as the connection PGND to SWI capacitor should be kept short and low resistive.
  • The compensation network for the Boost converter V(AVDD) must be placed as close as possible to the IC and connected by short lines to COMP and AGND to avoid noise coupling.
  • For V(IO) the line SWBK1, Diode, GND of INBK1 capacitor should be kept short and low resistive.
  • For V(CORE) an additional input capacitor should be used when the V(IO) output capacitor line is longer than 1 cm or a wide connection line is not possible to stabilize the input voltage.
  • Feedback lines starting at the output capacitors should be routed through a non noisy area away from switching traces. If possible the feedback lines should be kept short to reduce noise coupling.
  • Inductors can be placed further away from the IC to avoid IC heating through the inductor.
  • All IC Grounds (AGND, PGNDx) must be connected to the Exposed Thermal PAD.
  • Avoid vias in Power lines when possible because of their high inductance and resistance.
  • The Exposed Thermal PAD of the QFN package must be soldered to a big GND cooling area. For good thermal conduction to the cooling area as much as possible vias should be used to keep the device cool.
  • The thermal resistor NTC should be placed away from heat sources. For most accurate environment temperature measurement the NTC must be placed at the coldest point of the PCB.

10.2 Layout Example

TPS65177 TPS65177A Layout_Guide.gif Figure 48. Example Layout
TPS65177 TPS65177A EVM_schematic.gif
Options can be removed if not needed
Figure 49. Sample 2-layer Layout